Icestorm: FMLAL2 (vector, 2S) measurements

Code:

  fmlal2 v0.2s, v1.2h, v2.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fmlal2 v0.2s, v1.2h, v2.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10205	40066	10105	101	10004	100	10030	300	1028904	10130	200	10044	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  fmlal2 v0.2s, v0.2h, v1.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	307	1028904	10132	202	10046	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30141	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  fmlal2 v0.2s, v1.2h, v0.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10006	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1029107	10131	200	0	10044	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	0	100	10000	0	307	0	1029657	10164	202	0	10080	200	0	30135	1	0	10000	100
10204	40033	10101	101	10000	0	100	10000	0	307	0	1029026	10133	202	0	10042	2074	1408	30126	905	577	10002	1126
10204	40033	10101	101	10000	0	100	10000	0	300	0	1029107	10131	200	0	10044	200	0	30246	1	0	10000	100
10204	40136	10117	105	10012	0	104	10062	0	300	0	1028557	10100	200	0	10004	200	0	30249	1	0	10000	100
10204	40188	10119	101	10018	0	100	10093	0	300	0	1028557	10100	200	0	10004	200	0	30018	1	0	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlal2 v0.2s, v8.2h, v9.2h
  movi v1.16b, 0
  fmlal2 v1.2s, v8.2h, v9.2h
  movi v2.16b, 0
  fmlal2 v2.2s, v8.2h, v9.2h
  movi v3.16b, 0
  fmlal2 v3.2s, v8.2h, v9.2h
  movi v4.16b, 0
  fmlal2 v4.2s, v8.2h, v9.2h
  movi v5.16b, 0
  fmlal2 v5.2s, v8.2h, v9.2h
  movi v6.16b, 0
  fmlal2 v6.2s, v8.2h, v9.2h
  movi v7.16b, 0
  fmlal2 v7.2s, v8.2h, v9.2h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40480	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40110	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40096	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240150	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43847	80019	11	80008	10	80012	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41268	80011	11	80000	10	80000	30	320192	80057	20	80047	20	240000	1	160000	10
160024	40437	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40409	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40401	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40412	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40412	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40412	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40440	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40415	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  fmlal2 v0.2s, v12.2h, v13.2h
  fmlal2 v1.2s, v12.2h, v13.2h
  fmlal2 v2.2s, v12.2h, v13.2h
  fmlal2 v3.2s, v12.2h, v13.2h
  fmlal2 v4.2s, v12.2h, v13.2h
  fmlal2 v5.2s, v12.2h, v13.2h
  fmlal2 v6.2s, v12.2h, v13.2h
  fmlal2 v7.2s, v12.2h, v13.2h
  fmlal2 v8.2s, v12.2h, v13.2h
  fmlal2 v9.2s, v12.2h, v13.2h
  fmlal2 v10.2s, v12.2h, v13.2h
  fmlal2 v11.2s, v12.2h, v13.2h

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
120205	60125	120145	101	120044	100	120056	300	480044	120110	200	120014	200	0	360042	1	0	120000	100
120204	60036	120107	101	120006	100	120010	300	480044	120110	200	120014	200	0	360036	1	0	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360201	1	0	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60036	120105	101	120004	100	120008	300	480040	120109	200	120013	200	0	360036	1	0	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360045	1	0	120000	100
120204	60046	120107	101	120006	100	120010	300	480044	120110	200	120014	200	0	360036	1	0	120000	100
120205	60073	120147	101	120046	100	120058	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360039	1	0	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60120	120016	11	120005	10	120009	30	480044	120020	20	120014	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360192	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10

FMLAL2 (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations