Icestorm: FMLAL (by element, 4S) measurements

Code:

  fmlal v0.4s, v1.4h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fmlal v0.4s, v1.4h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40084	10107	101	10006	0	100	10031	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	202	30126	2	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1029107	10131	200	0	10044	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	30132	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
12103	53605	11858	1134	10008	716	1125	10060	70	1028557	10020	20	10004	20	30012	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30132	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30018	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  fmlal v0.4s, v0.4h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10205	40066	10105	101	10004	100	10030	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30126	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30225	11	10000	10
10024	40084	10027	21	10006	20	10031	0	70	0	1028557	10020	20	0	10000	20	30132	11	10000	10
10024	40084	10027	21	10006	20	10031	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40135	10033	21	10012	20	10062	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	68	0	1029657	10082	20	0	10077	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  fmlal v0.4s, v1.4h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10205	40066	10107	103	10004	102	10030	300	1028557	10100	200	10006	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	307	1028904	10132	202	10046	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30132	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30135	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	69	1028904	10050	20	10044	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	69	1028890	10050	20	10044	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	68	1028904	10050	20	10041	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	77	1028693	10038	22	10022	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlal v0.4s, v8.4h, v9.h[1]
  movi v1.16b, 0
  fmlal v1.4s, v8.4h, v9.h[1]
  movi v2.16b, 0
  fmlal v2.4s, v8.4h, v9.h[1]
  movi v3.16b, 0
  fmlal v3.4s, v8.4h, v9.h[1]
  movi v4.16b, 0
  fmlal v4.4s, v8.4h, v9.h[1]
  movi v5.16b, 0
  fmlal v5.4s, v8.4h, v9.h[1]
  movi v6.16b, 0
  fmlal v6.4s, v8.4h, v9.h[1]
  movi v7.16b, 0
  fmlal v7.4s, v8.4h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40507	80110	101	80009	0	100	80013	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40121	80110	101	80009	0	100	80013	300	320052	80112	200	80012	200	240039	1	160000	100
160204	40205	80144	101	80043	0	100	80047	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40094	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240138	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5056

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43779	80020	11	80009	10	80013	30	320056	80023	20	80013	20	240039	1	160000	10
160024	41249	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240147	1	160000	10
160024	40483	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40462	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40441	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40445	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40445	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40429	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40385	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40442	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  fmlal v0.4s, v12.4h, v13.h[1]
  fmlal v1.4s, v12.4h, v13.h[1]
  fmlal v2.4s, v12.4h, v13.h[1]
  fmlal v3.4s, v12.4h, v13.h[1]
  fmlal v4.4s, v12.4h, v13.h[1]
  fmlal v5.4s, v12.4h, v13.h[1]
  fmlal v6.4s, v12.4h, v13.h[1]
  fmlal v7.4s, v12.4h, v13.h[1]
  fmlal v8.4s, v12.4h, v13.h[1]
  fmlal v9.4s, v12.4h, v13.h[1]
  fmlal v10.4s, v12.4h, v13.h[1]
  fmlal v11.4s, v12.4h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120204	60068	120107	101	120006	100	120010	300	480044	120110	200	120014	200	360039	1	120000	100
120204	60046	120107	101	120006	100	120010	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480044	120110	200	120013	200	360039	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480212	120155	200	120065	200	360036	1	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60143	120018	11	120007	10	120011	0	30	0	480044	120020	20	0	120014	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360195	1	120000	10
120024	60047	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10

FMLAL (by element, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations