Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLA (vector, 4S)

Test 1: uops

Code:

  fmla v0.4s, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->1

Code:

  fmla v0.4s, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100000300010285571010020001000420030012110000100
10204402341012510110024100101240300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204402371012910510024104101240300010285571010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100042030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010289041005020100412030000111000010

Test 3: Latency 1->2

Code:

  fmla v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030012110000100
10204400331010110110000100100003001028557101002001000620030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000620030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100254006610025211000420100307010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010289041005020100402030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 4: Latency 1->3

Code:

  fmla v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003071028904101322021004620030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100042030018111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244008510027211000620100317010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  fmla v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  fmla v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  fmla v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  fmla v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  fmla v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  fmla v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  fmla v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044049480109101800081008001230032005680113200800132002400391160000100
1602044012180110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002401441160000100
1602044008680109101800081008001230032005280112200800122002401411160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244428480020118000910800133032005680023208001320240036116000010
1600244126280011118000010800003032000080010208000020240000116000010
1600244043280011118000010800003032000080010208000020240000116000010
1600244045080011118000010800003032000080010208000020240000116000010
1600244039180011118000010800003032000080010208000020240000116000010
1600244057180011118000010800003032000080010208000020240000116000010
1600244042680011118000010800003032000080010208000020240000116000010
1600244043380011118000010800003032000080010208000020240000116000010
1600244042880011118000010800003032000080010208000020240000116000010
1600244042580011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  fmla v0.4s, v16.4s, v17.4s
  fmla v1.4s, v16.4s, v17.4s
  fmla v2.4s, v16.4s, v17.4s
  fmla v3.4s, v16.4s, v17.4s
  fmla v4.4s, v16.4s, v17.4s
  fmla v5.4s, v16.4s, v17.4s
  fmla v6.4s, v16.4s, v17.4s
  fmla v7.4s, v16.4s, v17.4s
  fmla v8.4s, v16.4s, v17.4s
  fmla v9.4s, v16.4s, v17.4s
  fmla v10.4s, v16.4s, v17.4s
  fmla v11.4s, v16.4s, v17.4s
  fmla v12.4s, v16.4s, v17.4s
  fmla v13.4s, v16.4s, v17.4s
  fmla v14.4s, v16.4s, v17.4s
  fmla v15.4s, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800381601071011600061001600100300064004416011020001600142004800421160000100
160204800361601071011600061001600100300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160205800721601451011600441001600560300064004416011020001600132004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024800841600181116000710160011306400001600102016000020480000116000010
160024800531600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480195116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306402241600682016006520480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024801761600161116000510160009306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010