Icestorm: FMLSL2 (vector, 4S) measurements

Code:

  fmlsl2 v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fmlsl2 v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30012	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30132	11	10000	10

Test 3: Latency 1->2

Code:

  fmlsl2 v0.4s, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1029107	10131	200	10044	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028904	10050	20	10044	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  fmlsl2 v0.4s, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlsl2 v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  fmlsl2 v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  fmlsl2 v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  fmlsl2 v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  fmlsl2 v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  fmlsl2 v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  fmlsl2 v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  fmlsl2 v7.4s, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40492	80110	101	80009	100	80013	300	320056	80113	200	80013	200	0	240039	1	0	160000	100
160204	40118	80110	101	80009	100	80013	300	320052	80112	200	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240144	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	240036	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43798	80019	11	80008	10	80012	0	30	0	320056	80023	20	0	80013	20	240000	1	160000	10
160024	41230	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40435	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40424	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40428	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40416	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40424	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40454	80011	11	80000	10	80000	0	30	0	320196	80058	20	0	80048	20	240000	1	160000	10
160024	40448	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40397	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  fmlsl2 v0.4s, v12.4h, v13.4h
  fmlsl2 v1.4s, v12.4h, v13.4h
  fmlsl2 v2.4s, v12.4h, v13.4h
  fmlsl2 v3.4s, v12.4h, v13.4h
  fmlsl2 v4.4s, v12.4h, v13.4h
  fmlsl2 v5.4s, v12.4h, v13.4h
  fmlsl2 v6.4s, v12.4h, v13.4h
  fmlsl2 v7.4s, v12.4h, v13.4h
  fmlsl2 v8.4s, v12.4h, v13.4h
  fmlsl2 v9.4s, v12.4h, v13.4h
  fmlsl2 v10.4s, v12.4h, v13.4h
  fmlsl2 v11.4s, v12.4h, v13.4h

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120204	60081	120105	101	120004	100	120008	0	300	0	480044	120110	200	0	120014	200	360039	1	120000	100
120204	60046	120107	101	120006	100	120010	0	300	0	480044	120110	200	0	120013	200	360192	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	0	300	0	480036	120108	200	0	120012	200	360036	1	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60177	120015	11	120004	10	120008	30	480044	120020	20	120014	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10

FMLSL2 (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations