Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLSL2 (vector, 4S)

Test 1: uops

Code:

  fmlsl2 v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->1

Code:

  fmlsl2 v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100042030012111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030132111000010

Test 3: Latency 1->2

Code:

  fmlsl2 v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001029107101312001004420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100062030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100254006610025211000420100307010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010289041005020100442030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 4: Latency 1->3

Code:

  fmlsl2 v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100062030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlsl2 v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  fmlsl2 v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  fmlsl2 v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  fmlsl2 v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  fmlsl2 v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  fmlsl2 v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  fmlsl2 v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  fmlsl2 v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160204404928011010180009100800133003200568011320080013200024003910160000100
160204401188011010180009100800133003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024014410160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244379880019118000810800120300320056800232008001320240000116000010
1600244123080011118000010800000300320000800102008000020240000116000010
1600244043580011118000010800000300320000800102008000020240000116000010
1600244042480011118000010800000300320000800102008000020240000116000010
1600244042880011118000010800000300320000800102008000020240000116000010
1600244041680011118000010800000300320000800102008000020240000116000010
1600244042480011118000010800000300320000800102008000020240000116000010
1600244045480011118000010800000300320196800582008004820240000116000010
1600244044880011118000010800000300320000800102008000020240000116000010
1600244039780011118000010800000300320000800102008000020240000116000010

Test 6: throughput

Count: 12

Code:

  fmlsl2 v0.4s, v12.4h, v13.4h
  fmlsl2 v1.4s, v12.4h, v13.4h
  fmlsl2 v2.4s, v12.4h, v13.4h
  fmlsl2 v3.4s, v12.4h, v13.4h
  fmlsl2 v4.4s, v12.4h, v13.4h
  fmlsl2 v5.4s, v12.4h, v13.4h
  fmlsl2 v6.4s, v12.4h, v13.4h
  fmlsl2 v7.4s, v12.4h, v13.4h
  fmlsl2 v8.4s, v12.4h, v13.4h
  fmlsl2 v9.4s, v12.4h, v13.4h
  fmlsl2 v10.4s, v12.4h, v13.4h
  fmlsl2 v11.4s, v12.4h, v13.4h
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120204600811201051011200041001200080300048004412011020001200142003600391120000100
120204600461201071011200061001200100300048004412011020001200132003601921120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120024601771200151112000410120008304800441200202012001420360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010