Icestorm: FMLSL (by element, 2S) measurements

Code:

  fmlsl v0.2s, v1.2h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1005	4066	1005	1	1004	1030	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fmlsl v0.2s, v1.2h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30132	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  fmlsl v0.2s, v0.2h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10006	200	30126	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30132	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	391	7712	2847	892668	9737	931	446	8725	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  fmlsl v0.2s, v1.2h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30120	11	10000	10
10024	40033	10021	21	10000	20	10000	65	1028557	10020	20	10005	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlsl v0.2s, v8.2h, v9.h[1]
  movi v1.16b, 0
  fmlsl v1.2s, v8.2h, v9.h[1]
  movi v2.16b, 0
  fmlsl v2.2s, v8.2h, v9.h[1]
  movi v3.16b, 0
  fmlsl v3.2s, v8.2h, v9.h[1]
  movi v4.16b, 0
  fmlsl v4.2s, v8.2h, v9.h[1]
  movi v5.16b, 0
  fmlsl v5.2s, v8.2h, v9.h[1]
  movi v6.16b, 0
  fmlsl v6.2s, v8.2h, v9.h[1]
  movi v7.16b, 0
  fmlsl v7.2s, v8.2h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40495	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40108	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40228	80143	101	80042	100	80046	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40110	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43818	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41190	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40455	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40428	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40419	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40436	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40400	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40402	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40448	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  fmlsl v0.2s, v12.2h, v13.h[1]
  fmlsl v1.2s, v12.2h, v13.h[1]
  fmlsl v2.2s, v12.2h, v13.h[1]
  fmlsl v3.2s, v12.2h, v13.h[1]
  fmlsl v4.2s, v12.2h, v13.h[1]
  fmlsl v5.2s, v12.2h, v13.h[1]
  fmlsl v6.2s, v12.2h, v13.h[1]
  fmlsl v7.2s, v12.2h, v13.h[1]
  fmlsl v8.2s, v12.2h, v13.h[1]
  fmlsl v9.2s, v12.2h, v13.h[1]
  fmlsl v10.2s, v12.2h, v13.h[1]
  fmlsl v11.2s, v12.2h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120204	60062	120105	101	120004	100	120008	300	480208	120154	200	120062	200	360039	1	120000	100
120204	60036	120107	101	120006	100	120010	300	480044	120110	200	120014	200	360042	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480044	120110	200	120013	200	360036	1	120000	100
120205	60073	120147	101	120046	100	120058	300	480036	120108	200	120012	200	360036	1	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
120024	60329	120016	11	120005	10	120009	30	480052	120022	20	120015	20	0	360042	1	0	120000	10
120025	60100	120054	11	120043	10	120055	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120024	60042	120011	11	120000	10	120000	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120024	60042	120011	11	120000	10	120000	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120024	60042	120011	11	120000	10	120000	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120024	60042	120011	11	120000	10	120000	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120025	60079	120054	11	120043	10	120055	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120024	60042	120011	11	120000	10	120000	30	480000	120010	20	120000	20	0	360000	1	0	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	0	360000	1	0	120000	10

FMLSL (by element, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations