Icestorm: FMLS (by element, 2D) measurements

Code:

  fmls v0.2d, v1.2d, v2.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fmls v0.2d, v1.2d, v2.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10205	40066	10105	101	10004	0	100	10030	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028904	10050	20	10044	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10

Test 3: Latency 1->2

Code:

  fmls v0.2d, v0.2d, v1.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30138	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028904	10050	20	10044	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  fmls v0.2d, v1.2d, v0.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30018	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	66	1028904	10050	20	10044	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.2d, v8.2d, v9.d[1]
  movi v1.16b, 0
  fmls v1.2d, v8.2d, v9.d[1]
  movi v2.16b, 0
  fmls v2.2d, v8.2d, v9.d[1]
  movi v3.16b, 0
  fmls v3.2d, v8.2d, v9.d[1]
  movi v4.16b, 0
  fmls v4.2d, v8.2d, v9.d[1]
  movi v5.16b, 0
  fmls v5.2d, v8.2d, v9.d[1]
  movi v6.16b, 0
  fmls v6.2d, v8.2d, v9.d[1]
  movi v7.16b, 0
  fmls v7.2d, v8.2d, v9.d[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40491	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40111	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40096	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43804	80019	11	80008	10	80012	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41334	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40394	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40412	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40413	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41408	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40498	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40499	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40431	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40402	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  fmls v0.2d, v12.2d, v13.d[1]
  fmls v1.2d, v12.2d, v13.d[1]
  fmls v2.2d, v12.2d, v13.d[1]
  fmls v3.2d, v12.2d, v13.d[1]
  fmls v4.2d, v12.2d, v13.d[1]
  fmls v5.2d, v12.2d, v13.d[1]
  fmls v6.2d, v12.2d, v13.d[1]
  fmls v7.2d, v12.2d, v13.d[1]
  fmls v8.2d, v12.2d, v13.d[1]
  fmls v9.2d, v12.2d, v13.d[1]
  fmls v10.2d, v12.2d, v13.d[1]
  fmls v11.2d, v12.2d, v13.d[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120204	60068	120108	101	120007	100	120011	300	480044	120110	200	120014	200	360039	1	120000	100
120204	60046	120107	101	120006	100	120010	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480216	120156	200	120066	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60193	120016	11	120005	10	120009	30	480044	120020	20	120014	20	360000	1	120000	10
120025	60078	120056	11	120045	10	120057	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360192	1	120000	10
120024	60039	120016	11	120005	10	120009	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10

FMLS (by element, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations