Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLS (by element, 4H)

Test 1: uops

Code:

  fmls v0.4h, v1.4h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->1

Code:

  fmls v0.4h, v1.4h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020540066101051011000410010030300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
100244003310021211000002010000701028557100202010004200300001101000010
100244003310021211000002010000701028904100502010044200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100254006610027231000402210029701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010

Test 3: Latency 1->2

Code:

  fmls v0.4h, v0.4h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
102044003310101101100000100100003001028557101002001000620030018110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028904101302001004420030132110000100
708328020699811268602610568863001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 4: Latency 1->3

Code:

  fmls v0.4h, v1.4h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10205400661010510110004100100303001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010307571014420101522030000111000010
100244003310021211000020100007010285571002020100002030012111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.4h, v8.4h, v9.h[1]
  movi v1.16b, 0
  fmls v1.4h, v8.4h, v9.h[1]
  movi v2.16b, 0
  fmls v2.4h, v8.4h, v9.h[1]
  movi v3.16b, 0
  fmls v3.4h, v8.4h, v9.h[1]
  movi v4.16b, 0
  fmls v4.4h, v8.4h, v9.h[1]
  movi v5.16b, 0
  fmls v5.4h, v8.4h, v9.h[1]
  movi v6.16b, 0
  fmls v6.4h, v8.4h, v9.h[1]
  movi v7.16b, 0
  fmls v7.4h, v8.4h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044048080110101800091008001330032005680113200800132002400391160000100
1602044011080110101800091008001330032005280112200800122002400361160000100
1602044009880110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602054013280143101800421008004630032005280112200800122002400361160000100
1602044011080110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032019680148200800482002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600254398180030118001910800273032000080010208000020240000116000010
1600244131780011118000010800003032000080010208000020240000116000010
1600244045080011118000010800003032020080059208004920240000116000010
1600244043180011118000010800003032000080010208000020240000116000010
1600244040980011118000010800003032000080010208000020240000116000010
1600244043880011118000010800003032000080010208000020240000116000010
1600244042680011118000010800003032000080010208000020240000116000010
1600244043780011118000010800003032000080010208000020240000116000010
1600244042780011118000010800003032000080010208000020240000116000010
1600244043580011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 12

Code:

  fmls v0.4h, v12.4h, v13.h[1]
  fmls v1.4h, v12.4h, v13.h[1]
  fmls v2.4h, v12.4h, v13.h[1]
  fmls v3.4h, v12.4h, v13.h[1]
  fmls v4.4h, v12.4h, v13.h[1]
  fmls v5.4h, v12.4h, v13.h[1]
  fmls v6.4h, v12.4h, v13.h[1]
  fmls v7.4h, v12.4h, v13.h[1]
  fmls v8.4h, v12.4h, v13.h[1]
  fmls v9.4h, v12.4h, v13.h[1]
  fmls v10.4h, v12.4h, v13.h[1]
  fmls v11.4h, v12.4h, v13.h[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120204600861201071011200061001200103004800441201102001200142003600391120000100
120204600361201071011200061001200103004802241201582001200662003600421120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100
120204600361201051011200041001200083004800361201082001200122003600361120000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120024602821200151112000410120008304800441200202012001420360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360192112000010
120024601461200171112000610120010304800001200102012000020360000112000010