Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLS (by element, 4S)

Test 1: uops

Code:

  fmls v0.4s, v1.4s, v2.s[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->1

Code:

  fmls v0.4s, v1.4s, v2.s[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030132110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 3: Latency 1->2

Code:

  fmls v0.4s, v0.4s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1020440033101011011000010010000300102855710100200100062000300181010000100
1020440033101011011000010010000300102855710100200100062000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102889010130200100452000300151010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100
1020440033101011011000010010000300102855710100200100042000300121010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100006910285571002020100042030018111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 4: Latency 1->3

Code:

  fmls v0.4s, v1.4s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100000700102855710020200100062030000111000010
100244003310021211000020100000650102890410050200100382030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.4s, v8.4s, v9.s[1]
  movi v1.16b, 0
  fmls v1.4s, v8.4s, v9.s[1]
  movi v2.16b, 0
  fmls v2.4s, v8.4s, v9.s[1]
  movi v3.16b, 0
  fmls v3.4s, v8.4s, v9.s[1]
  movi v4.16b, 0
  fmls v4.4s, v8.4s, v9.s[1]
  movi v5.16b, 0
  fmls v5.4s, v8.4s, v9.s[1]
  movi v6.16b, 0
  fmls v6.4s, v8.4s, v9.s[1]
  movi v7.16b, 0
  fmls v7.4s, v8.4s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044051980109101800081008001230032005680113200800132002400391160000100
1602044012880110101800091008001330032005680113200800132002400361160000100
1602054012280145101800441008004830032005280112200800122002400391160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400391160000100
1602044009880109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005680113200800132002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600254399480055118004410800483032005680023208001320240000116000010
1600244132080011118000010800003032000080010208000020240000116000010
1600244039180011118000010800003032020080059208004920240000116000010
1600244042880011118000010800003032000080010208000020240000116000010
1600244036180011118000010800003032000080010208000020240000116000010
1600244039780011118000010800003032000080010208000020240000116000010
1600244036580011118000010800003032000080010208000020240000116000010
1600244043280011118000010800003032000080010208000020240000116000010
1600244043280011118000010800003032000080010208000020240000116000010
1600244043280011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 12

Code:

  fmls v0.4s, v12.4s, v13.s[1]
  fmls v1.4s, v12.4s, v13.s[1]
  fmls v2.4s, v12.4s, v13.s[1]
  fmls v3.4s, v12.4s, v13.s[1]
  fmls v4.4s, v12.4s, v13.s[1]
  fmls v5.4s, v12.4s, v13.s[1]
  fmls v6.4s, v12.4s, v13.s[1]
  fmls v7.4s, v12.4s, v13.s[1]
  fmls v8.4s, v12.4s, v13.s[1]
  fmls v9.4s, v12.4s, v13.s[1]
  fmls v10.4s, v12.4s, v13.s[1]
  fmls v11.4s, v12.4s, v13.s[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120204600541201061011200051001200090300048004412011020001200142003600421120000100
120204600361201071011200061001200100300048004412011020001200142003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120205600721201431011200421001200540300048003612010820001200122003600391120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100
120204600361201051011200041001200080300048003612010820001200122003600361120000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120024601881200161112000510120009304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600521200181112000710120011304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010
120024600361200111112000010120000304800001200102012000020360000112000010