Icestorm: FMLS (by element, S) measurements

Code:

  fmls s0, s1, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fmls s0, s1, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30138	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30012	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  fmls s0, s0, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10205	40066	10105	101	10004	100	10030	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10026	40099	10029	21	10008	20	10060	70	1028904	10050	20	10044	20	30015	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  fmls s0, s1, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	202	30138	2	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30132	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	67	1028904	10050	20	10043	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40084	10027	21	10006	20	10031	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls s0, s8, v9.s[1]
  movi v1.16b, 0
  fmls s1, s8, v9.s[1]
  movi v2.16b, 0
  fmls s2, s8, v9.s[1]
  movi v3.16b, 0
  fmls s3, s8, v9.s[1]
  movi v4.16b, 0
  fmls s4, s8, v9.s[1]
  movi v5.16b, 0
  fmls s5, s8, v9.s[1]
  movi v6.16b, 0
  fmls s6, s8, v9.s[1]
  movi v7.16b, 0
  fmls s7, s8, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40491	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	200	240039	1	160000	100
160204	40110	80110	101	80009	100	80013	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320204	80150	200	0	80050	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43905	80020	11	80009	10	80013	30	320056	80023	20	80013	20	240039	1	160000	10
160024	41313	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160025	40495	80056	11	80045	10	80049	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40430	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40406	80011	11	80000	10	80000	30	320196	80058	20	80048	20	240000	1	160000	10
160024	40441	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40446	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40445	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40400	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  fmls s0, s12, v13.s[1]
  fmls s1, s12, v13.s[1]
  fmls s2, s12, v13.s[1]
  fmls s3, s12, v13.s[1]
  fmls s4, s12, v13.s[1]
  fmls s5, s12, v13.s[1]
  fmls s6, s12, v13.s[1]
  fmls s7, s12, v13.s[1]
  fmls s8, s12, v13.s[1]
  fmls s9, s12, v13.s[1]
  fmls s10, s12, v13.s[1]
  fmls s11, s12, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120204	60085	120105	101	120004	100	120008	300	480044	120110	200	120014	200	360042	1	120000	100
120204	60036	120107	101	120006	100	120010	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360039	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60036	120105	101	120004	100	120008	300	480216	120156	200	120064	200	360036	1	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60482	120017	11	120006	10	120010	30	480044	120020	20	120014	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480224	120068	20	120064	20	360000	1	120000	10
120024	60036	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10

FMLS (by element, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations