Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLS (vector, 8H)

Test 1: uops

Code:

  fmls v0.8h, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->1

Code:

  fmls v0.8h, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0339

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028904101302001004220030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100254006610025211000420100307010285571002020100042030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 3: Latency 1->2

Code:

  fmls v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10024400331002121100002010000701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010
10025400661002521100042010030701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010
10024400331002121100002010000701028557100202010000200300001101000010

Test 4: Latency 1->3

Code:

  fmls v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010289041005020100442030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.8h, v8.8h, v9.8h
  movi v1.16b, 0
  fmls v1.8h, v8.8h, v9.8h
  movi v2.16b, 0
  fmls v2.8h, v8.8h, v9.8h
  movi v3.16b, 0
  fmls v3.8h, v8.8h, v9.8h
  movi v4.16b, 0
  fmls v4.8h, v8.8h, v9.8h
  movi v5.16b, 0
  fmls v5.8h, v8.8h, v9.8h
  movi v6.16b, 0
  fmls v6.8h, v8.8h, v9.8h
  movi v7.16b, 0
  fmls v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044051180109101800081008001230032005680113200800132002400391160000100
1602044012180110101800091008001330032005280112200800122002400391160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602054012280143101800421008004630032005680113200800132002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602054012380146101800451008004930032005280112200800122002400391160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044010580109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244383280019118000810800123032000080010208000020240000116000010
1600244117580011118000010800003032000080010208000020240000116000010
1600244041980011118000010800003032000080010208000020240000116000010
1600244042380011118000010800003032000080010208000020240000116000010
1600244041980011118000010800003032000080010208000020240000116000010
1600244041980011118000010800003032000080010208000020240000116000010
1600244041980011118000010800003032000080010208000020240000116000010
1600244042380011118000010800003032000080010208000020240000116000010
1600244041480011118000010800003032000080010208000020240144116000010
1600244048080011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  fmls v0.8h, v16.8h, v17.8h
  fmls v1.8h, v16.8h, v17.8h
  fmls v2.8h, v16.8h, v17.8h
  fmls v3.8h, v16.8h, v17.8h
  fmls v4.8h, v16.8h, v17.8h
  fmls v5.8h, v16.8h, v17.8h
  fmls v6.8h, v16.8h, v17.8h
  fmls v7.8h, v16.8h, v17.8h
  fmls v8.8h, v16.8h, v17.8h
  fmls v9.8h, v16.8h, v17.8h
  fmls v10.8h, v16.8h, v17.8h
  fmls v11.8h, v16.8h, v17.8h
  fmls v12.8h, v16.8h, v17.8h
  fmls v13.8h, v16.8h, v17.8h
  fmls v14.8h, v16.8h, v17.8h
  fmls v15.8h, v16.8h, v17.8h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801041601051011600041001600083006400441601102001600142004800391160000100
160204800461601071011600061001600103006400361601082001600122004800391160000100
160204800461601071011600061001600103006400361601082001600122004801921160000100
160204800461601071011600061001600103006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400441601102001600132004800391160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006402241601582001600682004800391160000100
160204800361601051011600041001600083006400361601082001600122004800421160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248023016001711160006010160010306400001600102016000020480195116000010
1600248009616001111160000010160000306400001600102016000020480042116000010
1600248004016001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248004416001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010