Icestorm: FMOV (D[1] from X) measurements

Code:

  fmov v0.d[1], x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  fmov v0.d[1], x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 9.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	90030	40101	10101	20000	10000	100	20000	10001	300	1376328	2318460	30101	200	10002	20004	200	10002	30006	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90092	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90110	40101	10101	20000	10000	100	20000	10000	300	1376651	2318980	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 9.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376320	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30025	90116	40017	10012	20003	10002	10	20028	10018	30	1377069	2319671	30057	20	10021	20041	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1377185	2319812	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  fmov v0.d[1], x8
  fmov v1.d[1], x8
  fmov v2.d[1], x8
  fmov v3.d[1], x8
  fmov v4.d[1], x8
  fmov v5.d[1], x8
  fmov v6.d[1], x8
  fmov v7.d[1], x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40633	160239	103	80067	80069	102	80098	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	160024	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	40366	160025	11	80006	80008	10	80012	80000	30	240000	640000	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	40060	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	40045	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80054	160108	1	80000	80000	10
160024	40113	160011	11	80000	80000	10	80000	80000	30	283124	699026	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	40047	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	40048	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	40050	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	40045	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80054	160108	1	80000	80000	10
160024	40049	160011	11	80000	80000	10	80000	80000	30	249224	657177	160010	20	80000	80000	20	80000	160000	1	80000	80000	10
160024	40045	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	160000	1	80000	80000	10

FMOV (D[1] from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations