Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMOV (D[1] from X)

Test 1: uops

Code:

  fmov v0.d[1], x0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000
2004203520011100010001000100030005031420001000100010002000110001000

Test 2: Latency 1->2 roundtrip

Code:

  fmov v0.d[1], x0
  fmov x0, d0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 9.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
302049003040101101012000010000100200001000130013763282318460301012001000220004200100023000610001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100
302049009240101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100
302049011040101101012000010000100200001000030013766512318980301002001000220002200100023000310001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100023000310001100001000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 9.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
30024900304001110011200001000010200001000030137632023184603001020100002000020100003000010001100001000010010
30025901164001710012200031000210200281001830137706923196713005720100212004120100003000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100003000010001100001000010010
30024900304001110011200001000010200001000030137718523198123001020100002000020100003000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100003000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100003000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100003000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100003000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100003000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100003000010001100001000010010

Test 3: throughput

Count: 8

Code:

  fmov v0.d[1], x8
  fmov v1.d[1], x8
  fmov v2.d[1], x8
  fmov v3.d[1], x8
  fmov v4.d[1], x8
  fmov v5.d[1], x8
  fmov v6.d[1], x8
  fmov v7.d[1], x8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160204406331602391038006780069102800988001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100
160204400901601151018000680008100800128001230024003664008016012420080012800122008001216002418000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160024403661600251180006800081080012800003024000064000016001020800008000020800001600001800008000010
160024400601600111180000800001080000800003024000064000016001020800008000020800001600001800008000010
160024400451600111180000800001080000800003024000064000016001020800008000020800541601081800008000010
160024401131600111180000800001080000800003028312469902616001020800008000020800001600001800008000010
160024400471600111180000800001080000800003024000064000016001020800008000020800001600001800008000010
160024400481600111180000800001080000800003024000064000016001020800008000020800001600001800008000010
160024400501600111180000800001080000800003024000064000016001020800008000020800001600001800008000010
160024400451600111180000800001080000800003024000064000016001020800008000020800541601081800008000010
160024400491600111180000800001080000800003024922465717716001020800008000020800001600001800008000010
160024400451600111180000800001080000800003024000064000016001020800008000020800001600001800008000010