Icestorm: FMOV (D to X) measurements

Code:

  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000

Test 2: Latency 1->2 roundtrip

Code:

  fmov x0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10003	10003	200	10003	10003	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10003	10003	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10021	300	1230510	899505	20136	200	10026	10026	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	70036	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20025	70087	30017	10013	10002	10002	10	10015	10000	30	1248940	899420	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70033	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10021	30	1248258	899505	20046	20	10026	10026	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010

Test 3: throughput

Count: 8

Code:

  fmov x0, d8
  fmov x1, d8
  fmov x2, d8
  fmov x3, d8
  fmov x4, d8
  fmov x5, d8
  fmov x6, d8
  fmov x7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	202	80038	80016	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80024	80035	160012	80011	80001	10	80003	30	320005	80011	20	80008	20	80000	80001	80010
80025	80070	160044	80025	80019	10	80025	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010
80024	80034	160011	80011	80000	10	80000	30	320000	80010	20	80000	20	80000	80001	80010

FMOV (D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations