Icestorm: FMOV (H from W) measurements

Code:

  fmov h0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	585	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Code:

  fmov h0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	70030	30101	10101	10000	10000	100	10000	10001	300	1219131	899398	20101	200	10003	10003	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10026	10026	10003	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10021	300	1245216	899557	20136	202	10025	10025	200	10002	10002	10001	10000	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219148	899411	20100	200	10002	10002	200	10002	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	70034	30011	10011	10000	10000	10	10000	10000	30	1218854	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10021	30	1221012	899557	20046	20	10026	10026	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10026	10026	10003	10000	10010
20024	70052	30011	10011	10000	10000	10	10000	10000	30	1218878	899411	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1219904	900152	20010	20	10000	10000	20	10000	10000	10001	10000	10010

Test 3: throughput

Count: 8

Code:

  fmov h0, w8
  fmov h1, w8
  fmov h2, w8
  fmov h3, w8
  fmov h4, w8
  fmov h5, w8
  fmov h6, w8
  fmov h7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40083	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40039	80107	101	80006	100	80010	300	240030	80110	200	80014	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80024	40160	80013	11	80002	10	80008	30	240024	80018	20	80012	20	80000	1	80000	10
80024	40033	80011	11	80000	10	80144	30	281032	80154	20	80171	20	80000	1	80000	10
80024	40036	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40033	80011	11	80000	10	80000	30	269898	80010	20	80000	20	80000	1	80000	10
80024	40033	80011	11	80000	10	80192	30	266206	80202	20	80228	20	80000	1	80000	10
80024	40036	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40033	80011	11	80000	10	80000	30	326988	80010	20	80000	20	80000	1	80000	10
80024	40036	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40033	80011	11	80000	10	80000	30	282918	80010	20	80000	20	80000	1	80000	10
80024	40042	80011	11	80000	10	80000	30	544356	80010	20	80000	20	80000	1	80000	10

FMOV (H from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations