Icestorm: FMOV (S from W) measurements

Code:

  fmov s0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	540	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	4560	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000
1004	533	1001	1	1000	1000	3000	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Code:

  fmov s0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20204	70030	30101	10101	10000	10000	100	10000	10001	300	1219131	899398	20101	200	10003	10003	200	10003	10003	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10021	300	1229676	899557	20136	200	10026	10026	200	10002	10002	10001	10000	0	10100
20205	70062	30110	10105	10003	10002	102	10015	10000	300	1219418	899606	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100
20204	70030	30101	10101	10000	10000	100	10000	10000	300	1219130	899398	20100	200	10002	10002	200	10002	10002	10001	10000	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	70038	30011	10011	10000	10000	10	10000	10000	30	1218854	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10021	30	1230246	899557	20046	20	10026	10026	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218860	899398	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70030	30011	10011	10000	10000	10	10000	10000	30	1218968	899476	20010	20	10000	10000	20	10000	10000	10001	10000	10010

Test 3: throughput

Count: 8

Code:

  fmov s0, w8
  fmov s1, w8
  fmov s2, w8
  fmov s3, w8
  fmov s4, w8
  fmov s5, w8
  fmov s6, w8
  fmov s7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40086	80105	101	80004	100	80056	300	240321	80156	200	80069	200	80014	1	80000	100
80204	40039	80107	101	80006	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40037	80105	101	80004	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100
80204	40112	80101	101	80000	100	80008	300	324798	80108	200	80012	200	80012	1	80000	100
80204	40040	80101	101	80000	100	80008	300	240024	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80024	40191	80017	11	80006	10	80010	30	240030	80020	20	80014	20	80000	1	80000	10
80024	40063	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	240000	80010	20	80000	20	80000	1	80000	10

FMOV (S from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations