Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMOV (S to W)

Test 1: uops

Code:

  fmov w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000
100410342001100110001000400010001000100010011000

Test 2: Latency 1->2 roundtrip

Code:

  fmov w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
202047003230101101011000010000100100001002030012366778995052013520010025100252001000310003100011000010100
202047009630101101011000010000100100001000030012489588994332010020010002100022001000210002100011000010100
202047003530101101011000010000100100001000030012488688993682010020010002100022001000210002100011000010100
202047003230101101011000010000100100001000030012488688993682010020010002100022001000210002100011000010100
202047003230101101011000010000100100001000030012488688993682010020010002100022001000210002100011000010100
202047003230101101011000010000100100001000030012488688993682010020010002100022001000210002100011000010100
202067024330116101071000510004102100301000030012488688993682010020010002100022001000210002100011000010100
202047003230101101011000010000100100001000030012488688993682010020010002100022001000210002100011000010100
202057006230107101031000210002100100151000030012488688993682010020010002100022001000210002100011000010100
202047003230101101011000010000100100001000030012488688993682010020010002100022001000210002100011000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
20024700333001110011100001000010100001000030124886889936820010201000010000201000010000100011000010010
20025700623001710013100021000210100151000030124913889956320010201000010000201000010000100011000010010
20024700323001110011100001000010100001000030124886889936820010201000010000201000010000100011000010010
20024700323001110011100001000010100001000030124886889936820010201000010000201000010000100011000010010
20024700323001110011100001000010100001000030124886889936820010201000010000201000010000100011000010010
20024700323001110011100001000010100001000030124886889936820010201000010000201000010000100011000010010
20024700323001110011100001000010100001000030124943689977920010201000010000201000010000100011000010010
20024700333001110011100001000010100001000030124888689938120010201000010000201000010000100011000010010
20024700343001110011100001000010100001000030124886889936820010201000010000201002610026100031000010010
20024700323001110011100001000010100001000030124886889936820010201000010000201000010000100011000010010

Test 3: throughput

Count: 8

Code:

  fmov w0, s8
  fmov w1, s8
  fmov w2, s8
  fmov w3, s8
  fmov w4, s8
  fmov w5, s8
  fmov w6, s8
  fmov w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
80204800471601018010180000100800013003200058010120080008200800088000180100
80205800691601338011580018100800243003200058010120080008200800088000180100
80204800341601018010180000100800013003200058010120080008200800088000180100
80204800341601018010180000100800013003200058010120080008200800088000180100
80204800341601018010180000100800013003200058010120080008200800088000180100
80204800341601018010180000100800013003200058010120080008200800088000180100
80204800341601018010180000100800013003200058010120080008200800088000180100
80204800341601018010180000100800013003200058010120080008200800088000180100
80204800401601018010180000100800013003200058010120080008200800088000180100
80204800341601018010180000100800013003200058010120080008200800088000180100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
8002480047160011800118000010800013032000080010208000020800008000180010
8002480034160011800118000010800003032000080010208000020800008000180010
8002580070160044800258001910800253032000080010208000020800008000180010
8002480034160011800118000010800003032000080010208000020800008000180010
8002480034160011800118000010800003032000080010208000020800008000180010
8002480034160011800118000010800003032000080010208000020800008000180010
8002480034160011800118000010800003032000080010208000020800008000180010
8002480034160011800118000010800003032000080010208000020800008000180010
8002580069160043800258001810800243032000080010208000020800008000180010
8002480034160011800118000010800003032009280034208003920800008000180010