Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMOV (scalar, immediate, S)

Test 1: uops

Code:

  fmov s0, #1.0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	? int output thing (e9)	? simd retires (ee)
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000

Test 2: throughput

Count: 8

Code:

  fmov s0, #1.0
  fmov s1, #1.0
  fmov s2, #1.0
  fmov s3, #1.0
  fmov s4, #1.0
  fmov s5, #1.0
  fmov s6, #1.0
  fmov s7, #1.0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40035	80108	101	80007	100	80011	300	320044	80110	200	80014	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320052	80112	200	80015	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320052	80112	200	80015	200	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40154	80029	21	80008	20	80012	68	320052	80032	20	80018	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10
80025	40069	80063	21	80042	20	80054	70	320000	80020	20	80000	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	11	80000	10