Icestorm: FMOV (vector, immediate, 4H) measurements

Code:

  fmov v0.4h, #1.0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	? int output thing (e9)	? simd retires (ee)
1004	539	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000
1004	534	1001	1	1000	1000	4000	1000	1000	1	1000

Count: 8

Code:

  fmov v0.4h, #1.0
  fmov v1.4h, #1.0
  fmov v2.4h, #1.0
  fmov v3.4h, #1.0
  fmov v4.4h, #1.0
  fmov v5.4h, #1.0
  fmov v6.4h, #1.0
  fmov v7.4h, #1.0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40054	80105	101	80004	100	80008	300	320044	80110	200	80014	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40130	80016	11	80005	10	80009	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10
80024	40034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	1	80000	10

FMOV (vector, immediate, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations