Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMOV (vector, immediate, 4S)

Test 1: uops

Code:

  fmov v0.4s, #1.0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)? int output thing (e9)? simd retires (ee)
1004572100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000

Test 2: throughput

Count: 8

Code:

  fmov v0.4s, #1.0
  fmov v1.4s, #1.0
  fmov v2.4s, #1.0
  fmov v3.4s, #1.0
  fmov v4.4s, #1.0
  fmov v5.4s, #1.0
  fmov v6.4s, #1.0
  fmov v7.4s, #1.0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400458010710180006100800103003200448011020080014200180000100
80205400698014310180042100800543003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100
80204400348010510180004100800083003200368010820080012200180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244010180027218000620800107032000080020208000020118000010
800244003480021218000020800007032000080020208000020118000010
800244003480021218000020800007032000080020208000020118000010
800244003480021218000020800007032000080020208000020118000010
800244003480021218000020800007032000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800007032000080020208000020118000010
800244003480021218000020800007032000080020208000020118000010