Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMULX (scalar, D)

Test 1: uops

Code:

  fmulx d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10054066100511004103010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000

Test 2: Latency 1->2

Code:

  fmulx d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620020008110000100
10204400331010110110000100100003001028557101002001000420020012110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420220092210000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100042020000111000010
100254006610025211000420100307010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100006910289041005020100432020000111000010
100244003310021211000020100007010285571002020100002020000111000010

Test 3: Latency 1->3

Code:

  fmulx d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10205400731010510110004100100303001028557101002001000620020012110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100062020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100006910289041005020100442020000111000010

Test 4: throughput

Count: 8

Code:

  fmulx d0, d8, d9
  fmulx d1, d8, d9
  fmulx d2, d8, d9
  fmulx d3, d8, d9
  fmulx d4, d8, d9
  fmulx d5, d8, d9
  fmulx d6, d8, d9
  fmulx d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8020440054801061018000510080009300320044801102008001420001600281080000100
8020440036801071018000610080010300320036801082008001220001600241080000100
8020440036801051018000410080008300320036801082008001220001600241080000100
8020440036801051018000410080008300320036801082008001220001600241080000100
8020440036801051018000410080008300320036801082008001220001601281080000100
8020440036801051018000410080008300320036801082008001220001600241080000100
8020440036801051018000410080008300320036801082008001220001600241080000100
8020440036801051018000410080008300320036801082008001220001600241080000100
8020440036801051018000410080008300320036801082008001220001600241080000100
8020440036801051018000410080008300320036801082008001220001600241080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244015680027218000620800106532000080020208000020160034118000010
800244004680029218000820800126532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010