Icestorm: FMULX (vector, 2D) measurements

Code:

  fmulx v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fmulx v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	20012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1029107	10051	20	10040	20	20000	11	10000	10
10025	40116	10031	21	10010	20	10061	69	1029107	10051	20	10044	20	20000	11	10000	10
10024	40084	10027	21	10006	20	10031	68	1030207	10113	20	10112	20	20314	11	10000	10
10024	40083	10027	21	10006	20	10031	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40083	10027	21	10006	20	10031	70	1029107	10051	20	10038	20	20000	11	10000	10
10024	40083	10027	21	10006	20	10031	70	1029657	10082	20	10086	20	20160	11	10000	10
10024	40187	10041	23	10018	22	10093	68	1029657	10082	20	10080	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  fmulx v0.2d, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10006	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	0	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10006	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20090	11	10000	10
10024	40033	10021	21	10000	0	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  fmulx v0.2d, v8.2d, v9.2d
  fmulx v1.2d, v8.2d, v9.2d
  fmulx v2.2d, v8.2d, v9.2d
  fmulx v3.2d, v8.2d, v9.2d
  fmulx v4.2d, v8.2d, v9.2d
  fmulx v5.2d, v8.2d, v9.2d
  fmulx v6.2d, v8.2d, v9.2d
  fmulx v7.2d, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80205	40097	80143	101	80042	100	80054	300	320044	80110	200	80014	200	160026	1	80000	100
80204	40036	80107	101	80006	100	80010	300	320036	80108	200	80012	200	160028	1	80000	100
80204	40046	80107	101	80006	100	80010	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40142	80027	21	80006	20	80010	68	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40064	80030	21	80009	20	80013	68	320052	80032	20	80018	20	160036	11	80000	10
80024	40036	80029	21	80008	20	80012	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10

FMULX (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations