Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMUL (by element, 2D)

Test 1: uops

Code:

  fmul v0.2d, v0.2d, v1.d[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000

Test 2: Latency 1->2

Code:

  fmul v0.2d, v0.2d, v1.d[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10204400331010110110000010010000300102855710100200100062000200121010000100
10204400331010110110000010010000300102855710100200100042000200121010000100
10204400331010110110000010010000300102855710100200100042000200081010000100
10204400331010110110000010010000300102855710100200100042000200081010000100
10204400331010110110000010010000300102855710100200100042000200081010000100
10204400331010110110000010010000300102855710100200100042000200081010000100
10204400331010110110000010010000300102855710100200100042000200081010000100
10204400331010110110000010010000300102855710100200100042000200081010000100
10204400331010110110000010010000300102855710100200100042000200081010000100
10204400331010110110000010010000300102855710100200100042000200081010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010
100244003310021211000020100000700102855710020200100002020000111000010

Test 3: Latency 1->3

Code:

  fmul v0.2d, v1.2d, v0.d[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
102044003310101101100000100100003001028557101002001000620020008110000100
102044003310101101100000100100003001028557101002001000420020008110000100
102044003310101101100000100100003001028557101002001000420020008110000100
102044003310101101100000100100003001028557101002001000420020008110000100
102044003310101101100000100100003001028557101002001000420020008110000100
102044003310101101100000100100003001028557101002001000420020008110000100
102044003310101101100000100100003071028904101322021004620020008110000100
102044003310101101100000100100003001028904101302001004420020008110000100
102044003310101101100000100100003001028557101002001000620020008110000100
102044003310101101100000100100003001028557101002001000620020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100254006610025211000420100307010285571002020100002020000111000010
100254006610025211000420100307010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  fmul v0.2d, v8.2d, v9.d[1]
  fmul v1.2d, v8.2d, v9.d[1]
  fmul v2.2d, v8.2d, v9.d[1]
  fmul v3.2d, v8.2d, v9.d[1]
  fmul v4.2d, v8.2d, v9.d[1]
  fmul v5.2d, v8.2d, v9.d[1]
  fmul v6.2d, v8.2d, v9.d[1]
  fmul v7.2d, v8.2d, v9.d[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400868010710180006100800103003200448011020080014200160026180000100
80204400368010710180006100800103003200448011020080013200160028180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200448011020080013200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244011980030218000920800136832000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010