Icestorm: FMUL (scalar, D) measurements

Code:

  fmul d0, d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fmul d0, d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	202	20084	2	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20090	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10006	20	20008	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	571	30948	10242	1028894	11489	1212	672	10048	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	69	0	1028929	10050	20	0	10038	20	20082	11	10000	10

Test 3: Latency 1->3

Code:

  fmul d0, d1, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	0	300	0	1028904	10130	200	0	10042	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10006	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	67	1028839	10050	20	10043	20	20008	11	10000	10
10024	40033	10021	21	10000	20	10000	69	1028557	10020	20	10004	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20086	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  fmul d0, d8, d9
  fmul d1, d8, d9
  fmul d2, d8, d9
  fmul d3, d8, d9
  fmul d4, d8, d9
  fmul d5, d8, d9
  fmul d6, d8, d9
  fmul d7, d8, d9

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40049	80108	101	80007	100	80011	0	300	0	320044	80110	200	0	80014	200	160028	1	80000	100
80204	40036	80107	101	80006	100	80010	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160128	1	80000	100
80204	40036	80105	101	80004	100	80008	1427	59442	16635	323306	83741	3010	1762	80103	200	160026	1	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40204	80027	21	80006	20	80010	0	65	0	320052	80032	20	0	80017	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	64	0	320220	80077	20	0	80068	20	160138	11	80000	10
80024	40080	80029	21	80008	20	80012	0	67	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320224	80078	20	0	80068	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10

FMUL (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations