Icestorm: FMUL (vector, 8H) measurements

Code:

  fmul v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fmul v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20088	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10006	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	69	1028904	10050	20	10044	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  fmul v0.8h, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10205	40066	10105	101	10004	100	10030	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	68	1028904	10050	20	10044	20	0	20000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	20000	11	0	10000	10

Test 4: throughput

Count: 8

Code:

  fmul v0.8h, v8.8h, v9.8h
  fmul v1.8h, v8.8h, v9.8h
  fmul v2.8h, v8.8h, v9.8h
  fmul v3.8h, v8.8h, v9.8h
  fmul v4.8h, v8.8h, v9.8h
  fmul v5.8h, v8.8h, v9.8h
  fmul v6.8h, v8.8h, v9.8h
  fmul v7.8h, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40085	80105	101	80004	100	80008	300	320044	80110	200	80014	200	0	160028	1	0	80000	100
80204	40036	80107	101	80006	100	80010	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40036	80105	101	80004	100	80008	300	320224	80158	200	80068	200	0	160024	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40155	80028	21	80007	20	80011	0	68	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160132	11	80000	10
80024	40036	80021	21	80000	20	80000	0	65	0	320000	80020	20	0	80000	20	160000	11	80000	10

FMUL (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations