Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FNEG (vector, 4S)

Test 1: uops

Code:

  fneg v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000

Test 2: Latency 1->2

Code:

  fneg v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102042003310101101100001001000030050924810100200100062000100061010000100
102042003310101101100001001000030050924810100200100062000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100061010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100441010000100
10204200841011310110012100100363005092481010020010004308926211010015051298100322287
102042003310101101100001001000030050924810100200100042000100041010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100002010000111000010
10025200661002921100082010034705092471002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  fneg v0.4s, v8.4s
  fneg v1.4s, v8.4s
  fneg v2.4s, v8.4s
  fneg v3.4s, v8.4s
  fneg v4.4s, v8.4s
  fneg v5.4s, v8.4s
  fneg v6.4s, v8.4s
  fneg v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
802044003580107101800061008001003000320036801082000800122000800121080000100
802044003480107101800061008001003000320036801082000800122000800601080000100
802044003480105101800041008000803000320044801102000800142000800121080000100
802044003480105101800041008000803000320044801102000800142000800121080000100
802044003480105101800041008000803000320036801082000800122000800121080000100
802044003480105101800041008000803000320036801082000800122000800121080000100
802044003480105101800041008000803000320036801082000800122000800121080000100
802044003480105101800041008000803000320036801082000800122000800121080000100
802044003480105101800041008000803000320036801082000800122000800121080000100
802044003480105101800041008000803000320036801082000800122000800121080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024401438002921800082080012070032004480030200800162080000118000010
80024400348002121800002080000070032000080020200800002080000118000010
80024400348002121800002080000070032000080020200800002080000118000010
80024400348002121800002080000070032000080020200800002080000118000010
80024400348002121800002080000070032000080020200800002080000118000010
80024400348002121800002080000070032000080020200800002080000118000010
80024400348002121800002080000070032000080020200800002080065118000010
80024400348002121800002080000070032000080020200800002080000118000010
80024400348002121800002080000070032000080020200800002080000118000010
80024400348002121800002080000070032000080020200800002080000118000010