Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRECPE (vector, 8H)

Test 1: uops

Code:

  frecpe v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000

Test 2: Latency 1->2

Code:

  frecpe v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020440033101011011000010010000300509608101002001000420010006110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024400331002121100002010000070050960810020200100062010000111000010
10024400331002121100002010000070050960810020200100002010028111000010
10024400331002121100002010000070050960810020200100002010000111000010
10024400331002121100002010000070050960810020200100002010000111000010
10024400331002121100002010000070050960810020200100002010000111000010
10024400331002121100002010000070050960810020200100002010000111000010
10024400331002121100002010000070050960810020200100002010000111000010
10024400331002121100002010000070050960810020200100002010000111000010
10024400331002121100002010000070050960810020200100002010000111000010
10024400331002121100002010000070050960810020200100002010000111000010

Test 3: throughput

Count: 8

Code:

  frecpe v0.8h, v8.8h
  frecpe v1.8h, v8.8h
  frecpe v2.8h, v8.8h
  frecpe v3.8h, v8.8h
  frecpe v4.8h, v8.8h
  frecpe v5.8h, v8.8h
  frecpe v6.8h, v8.8h
  frecpe v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
802041600358010110180000010080000300199993280122200800322000800041080000100
802041600358010110180000010080000300199976980100200800042000800041080000100
8020416003580101101800000100800003001999932801222008003529762004800511417835800051731
802041600358010110180000010080000300199976980100200800042000800041080000100
802041600358010110180000010080000300199993280122200800362000800041080000100
802041600358010110180000010080000300199976980100200800042000800041080000100
802041600358010110180000010080000300199993280122200800322000800041080000100
802041600358010110180000010080000300199976980100200800042000800041080000100
802041600358010110180000010080000300199976980100200800042000800041080000100
802041600358010110180000010080000300199976980100200800042000800041080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8002416003580021218000020800007019997698002020800042080000118000010
8002416003580021218000020800007019999328004220800362080004118000010
8002416003580021218000020800007019997698002020800002080000118000010
8002416003580021218000020800007019997698002020800002080000118000010
8002416003580021218000020800007019997698002020800002080037118000010
8002416003580021218000020800007019997698002020800002080000118000010
8002416003580021218000020800007019997698002020800002080000118000010
8002416003580021218000020800007019997698002020800002080000118000010
8002416003580021218000020800007019997698002020800002080036118000010
8002416003580021218000020800007019997698002020800002080000118000010