Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRECPS (scalar, H)

Test 1: uops

Code:

  frecps h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000
10044033100111000100010155710001000200011000

Test 2: Latency 1->2

Code:

  frecps h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620020012110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020012110000100
10204400331010110110000100100003001028557101002001000620020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244023510045211002420101247010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100006910307571014420101572020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020088111000010

Test 3: Latency 1->3

Code:

  frecps h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620020012110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420020008110000100
10204400331010110110000100100003001028557101002001000420220088210000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100062020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010
100244003310021211000020100007010285571002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  frecps h0, h8, h9
  frecps h1, h8, h9
  frecps h2, h8, h9
  frecps h3, h8, h9
  frecps h4, h8, h9
  frecps h5, h8, h9
  frecps h6, h8, h9
  frecps h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400838010510180004100800083003200448011020080014200160028180000100
80204400368010510180004100800083003202088015420080061200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160128180000100
80204400368010710180006100800103003200368010820080012200160024180000100
80204400368010510180004100800083003200368010820080012200160024180000100
80205400728014710380044102800563003200448011020080013200160028180000100
80204400558010710180006100800103003200448011020080014200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244012080028218000720800116932000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010
800254007380067218004620800586532000080020208000020160000118000010
800244003680021218000020800006532000080020208000020160000118000010