Icestorm: FRECPS (vector, 8H) measurements

Code:

  frecps v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000
1004	4033	1001	1	1000	1000	0	0	0	101557	1000	0	0	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  frecps v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10205	40066	10107	103	10004	102	10030	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10004	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	66	1030757	10144	20	10152	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20160	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40084	10027	21	10006	20	10031	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40133	10033	21	10012	20	10062	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40135	10033	21	10012	20	10062	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	68	1029657	10082	20	10077	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1029107	10051	20	10038	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	69	1029107	10051	20	10038	22	20156	12	10000	10

Test 3: Latency 1->3

Code:

  frecps v0.8h, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40236	10045	21	10024	20	10124	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	20000	11	10000	10
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  frecps v0.8h, v8.8h, v9.8h
  frecps v1.8h, v8.8h, v9.8h
  frecps v2.8h, v8.8h, v9.8h
  frecps v3.8h, v8.8h, v9.8h
  frecps v4.8h, v8.8h, v9.8h
  frecps v5.8h, v8.8h, v9.8h
  frecps v6.8h, v8.8h, v9.8h
  frecps v7.8h, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40101	80105	101	80004	100	80008	300	320044	80110	200	80014	200	160028	1	80000	100
80204	40036	80107	101	80006	100	80010	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80205	40072	80143	101	80042	100	80054	300	320036	80108	200	80012	200	160026	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40036	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40186	80027	21	80006	0	20	80010	65	320052	80032	20	80017	20	160134	11	80000	10
80024	40046	80029	21	80008	0	20	80012	65	320052	80032	20	80017	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40036	80021	21	80000	0	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10

FRECPS (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations