Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRECPX (scalar, D)

Test 1: uops

Code:

  frecpx d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  frecpx d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10006	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	307	379850	10120	202	10034	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10025	30066	10027	21	10006	20	10018	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  frecpx d0, d8
  frecpx d1, d8
  frecpx d2, d8
  frecpx d3, d8
  frecpx d4, d8
  frecpx d5, d8
  frecpx d6, d8
  frecpx d7, d8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	80008	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	80035	80023	21	80002	20	80004	70	320100	80046	20	80038	20	80008	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80040	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320010	80022	20	80008	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80010	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10