Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRECPX (scalar, S)

Test 1: uops

Code:

  frecpx s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  frecpx s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10006	200	0	10006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	0	10004	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	0	10004	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	0	10004	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	0	10004	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	0	10059	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	0	10004	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	0	10032	1	0	10000	100
10206	30099	10113	101	10012	100	10036	300	379694	10100	200	10004	200	0	10004	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10006	200	0	10004	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10006	20	10004	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	68	379850	10038	20	10035	20	10000	11	10000	10
10026	30099	10033	21	10012	20	10036	70	379694	10020	20	10004	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10025	30058	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  frecpx s0, s8
  frecpx s1, s8
  frecpx s2, s8
  frecpx s3, s8
  frecpx s4, s8
  frecpx s5, s8
  frecpx s6, s8
  frecpx s7, s8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	80085	80126	101	80025	100	80028	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320110	80127	200	0	80038	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80085	80126	101	80025	100	80027	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80035	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	80050	80021	21	80000	20	80002	70	320010	80022	20	80008	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10