Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINT32X (vector, 2S)

Test 1: uops

Code:

  frint32x v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000

Test 2: Latency 1->2

Code:

  frint32x v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620010006110000100
1020430186101271031002410210099307769451101352021004420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430138101091011000810010033307769451101352021004620010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420210084210000100
1020430239101371051003210410132300768905101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002530066100292310006221003170768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010

Test 3: throughput

Count: 8

Code:

  frint32x v0.2s, v8.2s
  frint32x v1.2s, v8.2s
  frint32x v2.2s, v8.2s
  frint32x v3.2s, v8.2s
  frint32x v4.2s, v8.2s
  frint32x v5.2s, v8.2s
  frint32x v6.2s, v8.2s
  frint32x v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400748010710180006010080010300320036801082008001220080012180000100
80204400358010710180006010080010300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024400648002721800062080010703200528003220800182080016118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703208008022020802002080000118000010
80024400358002121800002080000703200008002020800002080000118000010