Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINT32Z (vector, 2S)

Test 1: uops

Code:

  frint32z v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004313610171101610667590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000

Test 2: Latency 1->2

Code:

  frint32z v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10205300661010710110006010010031300768905101002001000620010006110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100
10204300331010110110000010010000300768905101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002010000111000010
10024300331002121100002010000070076890510020200100002210046121000010

Test 3: throughput

Count: 8

Code:

  frint32z v0.2s, v8.2s
  frint32z v1.2s, v8.2s
  frint32z v2.2s, v8.2s
  frint32z v3.2s, v8.2s
  frint32z v4.2s, v8.2s
  frint32z v5.2s, v8.2s
  frint32z v6.2s, v8.2s
  frint32z v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020440083801051018000410080008300320036801082008001220080012180000100
8020440045801051018000410080008300320036801082008001220080014180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801071018000610080010300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80025402128006521800442080056703200528003220800182080000118000010
80024401248002721800062080010703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010