Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRINTI (scalar, D)

Test 1: uops

Code:

  frinti d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  frinti d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	10045	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	10004	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10006	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	175	10376	2963	769223	10509	440	204	10042	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	10004	11	10000	10
10024	30033	10021	21	10000	20	10000	0	66	0	769247	10051	20	0	10046	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  frinti d0, d8
  frinti d1, d8
  frinti d2, d8
  frinti d3, d8
  frinti d4, d8
  frinti d5, d8
  frinti d6, d8
  frinti d7, d8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40035	80107	101	80006	0	100	80010	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80107	101	80006	0	100	80010	300	320044	80110	200	80014	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40138	80029	21	80008	20	80012	70	320044	80030	20	80016	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10