Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
frintp v0.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 76982 | 1066 | 1082 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 1000 | 1 | 1000 |
Code:
frintp v0.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
16260 | 67574 | 15208 | 3625 | 9613 | 1970 | 3453 | 9638 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10006 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10006 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 0 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 10004 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10006 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 10000 | 11 | 10000 | 10 |
Count: 8
Code:
frintp v0.2d, v8.2d frintp v1.2d, v8.2d frintp v2.2d, v8.2d frintp v3.2d, v8.2d frintp v4.2d, v8.2d frintp v5.2d, v8.2d frintp v6.2d, v8.2d frintp v7.2d, v8.2d
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5004
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
80204 | 40036 | 80107 | 101 | 80006 | 100 | 80010 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80014 | 1 | 80000 | 100 |
80204 | 40035 | 80107 | 101 | 80006 | 100 | 80010 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80107 | 101 | 80006 | 100 | 80010 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
80204 | 40035 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 80012 | 1 | 80000 | 100 |
Result (median cycles for code divided by count): 0.5004
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
80024 | 40129 | 80029 | 21 | 80008 | 20 | 80012 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80066 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |
80024 | 40035 | 80021 | 21 | 80000 | 20 | 80000 | 0 | 70 | 0 | 320000 | 80020 | 20 | 0 | 80000 | 20 | 80000 | 11 | 80000 | 10 |