Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRSQRTE (scalar, D)

Test 1: uops

Code:

  frsqrte d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000

Test 2: Latency 1->2

Code:

  frsqrte d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300379694101002001000620010004110000100
1020430033101011011000010010000300379694101002001000620010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000703796941002020100002010000111000010
10024300331002121100002010000703796941002020100002010000111000010
10024300331002121100002010000703796941002020100002010000111000010
10024300331002121100002010000703796941002020100002010000111000010
10024300331002121100002010000703796941002020100002010000111000010
10024300331002121100002010000703796941002020100002010032111000010
10024300331002121100002010000703798501003820100322010004111000010
10024300331002121100002010000703796941002020100002010000111000010
10024300331002121100002010000703796941002020100002010000111000010
10024300331002121100002010000703796941002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  frsqrte d0, d8
  frsqrte d1, d8
  frsqrte d2, d8
  frsqrte d3, d8
  frsqrte d4, d8
  frsqrte d5, d8
  frsqrte d6, d8
  frsqrte d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
802048004980101101800001008000130032000580101200800082000800081080000100
802048003580101101800001008000130032000580101200800082000800081080000100
802058007080121101800201008002630032000580101200800082000800081080000100
802048003580101101800001008000130032000580101200800082000800081080000100
802048003580101101800001008000130032000580101200800082000800081080000100
802048003580101101800001008000130032000580101200800082000800081080000100
802048003580101101800001008000130032000580101200800082000800081080000100
802048003580101101800001008000130032000580101200800082000800081080000100
802048003580101101800001008000130032000580101200800082000800081080000100
802058007080120101800191008002530032000580101200800082000800081080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024800438002121800002080002703200008002020800002080040118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80025800708003921800182080022703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010