Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRSQRTE (vector, 2D)

Test 1: uops

Code:

  frsqrte v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000
1004403310011100010005060810001000100011000

Test 2: Latency 1->2

Code:

  frsqrte v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020440033101011011000010010000300509608101002001000620010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010032110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010032110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000300509608101002001000420010004110000100
1020440033101011011000010010000307509771101192021003020010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024400331002121100002010000705096081002020100062010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010
10024400331002121100002010000705096081002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  frsqrte v0.2d, v8.2d
  frsqrte v1.2d, v8.2d
  frsqrte v2.2d, v8.2d
  frsqrte v3.2d, v8.2d
  frsqrte v4.2d, v8.2d
  frsqrte v5.2d, v8.2d
  frsqrte v6.2d, v8.2d
  frsqrte v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
802041600358010110180000100800003001999932801222008003620080004180000100
802041600358010110180000100800003001999769801002008000420080004180000100
802041600358010110180000100800003001999769801002008000420080004180000100
802041600358010110180000100800003001999769801002008000420080004180000100
802051600708011010180009100800223001999932801222008003520080004180000100
802041600358010110180000100800003001999769801002008000420080004180000100
802041600358010110180000100800003002000095801442008006020080004180000100
802041600358010110180000100800003001999769801002008000420080004180000100
802041600358010110180000100800003001999769801002008000420080004180000100
802041600358010110180000100800003001999769801002008000420080036180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
800251600708003021800092080022070019997678002020080004200800041108000010
800241600358002121800002080000070019997698002020080000200800001108000010
800241600358002121800002080000070019997698002020080000200800001108000010
800241600358002121800002080000070019997698002020080000200800001108000010
800241600358002121800002080000070019997698002020080000200800001108000010
800241600358002121800002080000070019997698002020080000200800651108000010
800241600358002121800002080000070019997698002020080000200800001108000010
800241600358002121800002080000070019997698002020080000200800001108000010
800241600358002121800002080000070019997698002020080000200800001108000010
80024160035800212180000208000007001999932800422008003222871414800411105631800051295