Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FSQRT (scalar, D)

Test 1: uops

Code:

  fsqrt d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000
1004	13080	1003	1	1002	1015	167072	1015	1022	1024	1	1000
1004	13033	1001	1	1000	1000	166796	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fsqrt d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	130033	10101	101	10000	100	10000	300	1678796	10100	200	10006	200	10006	1	10000	100
10205	130066	10103	101	10002	100	10015	300	1678796	10100	200	10004	200	10004	1	10000	100
10204	130033	10101	101	10000	100	10000	300	1678968	10115	200	10028	202	10028	2	10000	100
10204	130033	10101	101	10000	100	10000	300	1678796	10100	200	10004	200	10004	1	10000	100
10204	130033	10101	101	10000	100	10000	300	1678796	10100	200	10004	200	10004	1	10000	100
10204	130033	10101	101	10000	100	10000	300	1678796	10100	200	10004	200	10004	1	10000	100
10204	130033	10101	101	10000	100	10000	300	1678796	10100	200	10004	200	10004	1	10000	100
10205	130066	10103	101	10002	100	10015	300	1678796	10100	200	10004	200	10004	1	10000	100
10204	130033	10101	101	10000	100	10000	300	1678796	10100	200	10004	200	10004	1	10000	100
10204	130033	10101	101	10000	100	10000	300	1678796	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	130033	10021	21	10000	20	10000	66	1678968	10035	20	10026	20	10006	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10004	20	10004	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10000	20	10000	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10000	20	10000	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10000	20	10028	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10000	20	10028	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10000	20	10000	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10000	20	10000	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678796	10020	20	10000	20	10000	11	10000	10
10024	130033	10021	21	10000	20	10000	70	1678968	10035	20	10028	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  fsqrt d0, d8
  fsqrt d1, d8
  fsqrt d2, d8
  fsqrt d3, d8
  fsqrt d4, d8
  fsqrt d5, d8
  fsqrt d6, d8
  fsqrt d7, d8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80040	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	2000044	80126	200	80036	200	80040	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80205	160088	80115	101	80014	0	100	80026	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160044	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	160044	80021	21	80000	0	20	80000	70	2000044	80046	20	80039	20	0	80004	11	0	80000	10
80024	160044	80021	21	80000	0	20	80000	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10
80024	160044	80021	21	80000	0	20	80000	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10
80024	160044	80021	21	80000	0	20	80000	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10
80025	160088	80035	21	80014	0	20	80026	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10
80024	160044	80021	21	80000	0	20	80000	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10
80024	160044	80021	21	80000	0	20	80000	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10
80025	160088	80035	21	80014	0	20	80026	70	1999769	80020	20	80000	1084	758	80046	436	285	80001	412
80024	160044	80021	21	80000	0	20	80000	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10
80024	160044	80021	21	80000	0	20	80000	70	1999769	80020	20	80000	20	0	80000	11	0	80000	10