Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FSQRT (scalar, D)

Test 1: uops

Code:

  fsqrt d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
100413033100111000100016679610001000100011000
100413033100111000100016679610001000100011000
100413033100111000100016679610001000100011000
100413033100111000100016679610001000100011000
100413033100111000100016679610001000100011000
100413033100111000100016679610001000100011000
100413033100111000100016679610001000100011000
100413033100111000100016679610001000100011000
100413080100311002101516707210151022102411000
100413033100111000100016679610001000100011000

Test 2: Latency 1->2

Code:

  fsqrt d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
102041300331010110110000100100003001678796101002001000620010006110000100
102051300661010310110002100100153001678796101002001000420010004110000100
102041300331010110110000100100003001678968101152001002820210028210000100
102041300331010110110000100100003001678796101002001000420010004110000100
102041300331010110110000100100003001678796101002001000420010004110000100
102041300331010110110000100100003001678796101002001000420010004110000100
102041300331010110110000100100003001678796101002001000420010004110000100
102051300661010310110002100100153001678796101002001000420010004110000100
102041300331010110110000100100003001678796101002001000420010004110000100
102041300331010110110000100100003001678796101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1002413003310021211000020100006616789681003520100262010006111000010
1002413003310021211000020100007016787961002020100042010004111000010
1002413003310021211000020100007016787961002020100002010000111000010
1002413003310021211000020100007016787961002020100002010000111000010
1002413003310021211000020100007016787961002020100002010028111000010
1002413003310021211000020100007016787961002020100002010028111000010
1002413003310021211000020100007016787961002020100002010000111000010
1002413003310021211000020100007016787961002020100002010000111000010
1002413003310021211000020100007016787961002020100002010000111000010
1002413003310021211000020100007016789681003520100282010000111000010

Test 3: throughput

Count: 8

Code:

  fsqrt d0, d8
  fsqrt d1, d8
  fsqrt d2, d8
  fsqrt d3, d8
  fsqrt d4, d8
  fsqrt d5, d8
  fsqrt d6, d8
  fsqrt d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020416004480101101800000100800003001999769801002008000420080040180000100
8020416004480101101800000100800003001999769801002008000420080004180000100
8020416004480101101800000100800003001999769801002008000420080004180000100
8020416004480101101800000100800003001999769801002008000420080004180000100
8020416004480101101800000100800003002000044801262008003620080040180000100
8020416004480101101800000100800003001999769801002008000420080004180000100
8020416004480101101800000100800003001999769801002008000420080004180000100
8020416004480101101800000100800003001999769801002008000420080004180000100
8020516008880115101800140100800263001999769801002008000420080004180000100
8020416004480101101800000100800003001999769801002008000420080004180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8002416004480021218000002080000702000044800462080039200800041108000010
8002416004480021218000002080000701999769800202080000200800001108000010
8002416004480021218000002080000701999769800202080000200800001108000010
8002416004480021218000002080000701999769800202080000200800001108000010
8002516008880035218001402080026701999769800202080000200800001108000010
8002416004480021218000002080000701999769800202080000200800001108000010
8002416004480021218000002080000701999769800202080000200800001108000010
800251600888003521800140208002670199976980020208000010847588004643628580001412
8002416004480021218000002080000701999769800202080000200800001108000010
8002416004480021218000002080000701999769800202080000200800001108000010