Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FSQRT (scalar, S)

Test 1: uops

Code:

  fsqrt s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fsqrt s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10006	200	0	10006	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289241	10115	200	10029	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10205	100066	10103	101	10002	0	100	10015	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10028	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10025	100066	10023	21	10002	20	10015	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  fsqrt s0, s8
  fsqrt s1, s8
  fsqrt s2, s8
  fsqrt s3, s8
  fsqrt s4, s8
  fsqrt s5, s8
  fsqrt s6, s8
  fsqrt s7, s8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	100	80000	300	2000007	80125	200	80036	200	80004	1	80000	100
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80036	1	80000	100
80204	160041	80101	101	80000	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80205	160082	80113	101	80012	100	80025	300	1999769	80100	200	80006	200	80004	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	70	2000007	80045	20	80036	20	80000	11	80000	10
80025	160082	80033	21	80012	20	80025	70	1999769	80020	20	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80036	11	80000	10
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	80000	11	80000	10