Icestorm: FSQRT (vector, 2D) measurements

Code:

  fsqrt v0.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000
1004	15033	1001	1	1000	1000	192614	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fsqrt v0.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 15.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10205	150066	10103	101	10002	100	10014	300	1938614	10100	200	10004	200	0	10006	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10004	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10004	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	202	0	10026	2	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10004	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10004	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10004	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10028	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10004	1	0	10000	100
10204	150033	10101	101	10000	100	10000	300	1938614	10100	200	10004	200	0	10004	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 15.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	150033	10021	21	10000	20	10000	68	1938786	10034	20	10025	20	10004	11	10000	10
10024	150033	10021	21	10000	20	10000	70	1938614	10020	20	10000	20	10000	11	10000	10
10024	150033	10021	21	10000	20	10000	68	1938786	10034	20	10028	20	10004	11	10000	10
10024	150033	10021	21	10000	20	10000	70	1938614	10020	20	10000	20	10028	11	10000	10
10024	150033	10021	21	10000	20	10000	70	1938614	10020	20	10000	20	10000	11	10000	10
10024	150033	10021	21	10000	20	10000	70	1938614	10020	20	10000	20	10000	11	10000	10
10025	150066	10023	21	10002	20	10014	70	1938614	10020	20	10000	20	10000	11	10000	10
10024	150033	10021	21	10000	20	10000	70	1938614	10020	20	10000	20	10000	11	10000	10
10024	150033	10021	21	10000	20	10000	70	1938614	10020	20	10000	20	10000	11	10000	10
10024	150033	10021	21	10000	20	10000	70	1938614	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  fsqrt v0.2d, v8.2d
  fsqrt v1.2d, v8.2d
  fsqrt v2.2d, v8.2d
  fsqrt v3.2d, v8.2d
  fsqrt v4.2d, v8.2d
  fsqrt v5.2d, v8.2d
  fsqrt v6.2d, v8.2d
  fsqrt v7.2d, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	320044	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	80004	1	80000	100
80205	320088	80108	101	80007	0	100	80020	0	300	0	4079608	80100	200	0	80004	200	80004	1	80000	100
80204	320044	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	80004	1	80000	100
80205	320088	80108	101	80007	0	100	80020	0	300	0	4079608	80100	200	0	80004	200	80036	1	80000	100
80204	320044	80101	101	80000	0	100	80000	0	300	0	4079911	80120	200	0	80032	200	80004	1	80000	100
80205	320088	80108	101	80007	0	100	80020	0	300	0	4079608	80100	200	0	80004	200	80034	1	80000	100
80204	320044	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	80004	1	80000	100
80205	320088	80108	101	80007	0	100	80020	0	300	0	4079608	80100	200	0	80004	200	80004	1	80000	100
80204	320044	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	80032	1	80000	100
95981	349623	96290	10821	80083	5386	10615	80122	0	300	0	4079911	80120	200	0	80036	200	80004	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	320044	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80036	11	0	80000	10
80025	320088	80028	21	80007	0	20	80020	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80025	320088	80028	21	80007	0	20	80020	70	4079608	80020	20	80000	20	0	80030	11	0	80000	10
80024	320044	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80024	320044	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80032	11	0	80000	10
80024	320044	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80024	320044	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80026	11	0	80000	10
80025	320088	80028	21	80007	0	20	80020	70	4079608	80020	20	80004	20	0	80000	11	0	80000	10
80024	320044	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80034	11	0	80000	10
80024	320044	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10

FSQRT (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations