Icestorm: FSQRT (vector, 2S) measurements

Code:

  fsqrt v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000
1004	10033	1001	1	1000	1000	0	0	0	128069	1000	0	0	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fsqrt v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10006	200	10030	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289241	10115	200	0	10032	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289241	10115	200	0	10028	200	10004	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10006	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10025	100066	10023	21	10002	20	10015	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10028	11	10000	10

Test 3: throughput

Count: 8

Code:

  fsqrt v0.2s, v8.2s
  fsqrt v1.2s, v8.2s
  fsqrt v2.2s, v8.2s
  fsqrt v3.2s, v8.2s
  fsqrt v4.2s, v8.2s
  fsqrt v5.2s, v8.2s
  fsqrt v6.2s, v8.2s
  fsqrt v7.2s, v8.2s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80205	160082	80113	101	80012	0	100	80025	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160328	80181	101	80080	0	100	80135	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80036	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80040	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	2000007	80125	200	80040	200	80004	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160041	80101	101	80000	0	100	80000	300	2000007	80125	200	80040	200	80004	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80004	11	80000	10
80025	160082	80033	21	80012	20	80025	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80037	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80038	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	2000007	80045	20	0	80040	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160041	80021	21	80000	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10

FSQRT (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations