Icestorm: FSQRT (vector, 4S) measurements

Code:

  fsqrt v0.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1005	12066	1003	1	1002	1015	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000
1004	12033	1001	1	1000	1000	153887	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fsqrt v0.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10006	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10006	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10004	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10004	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10004	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10004	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10004	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10004	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1548887	10100	200	10004	200	10004	1	10000	100
10204	120033	10101	101	10000	100	10000	300	1549059	10115	200	10032	200	10032	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	120033	10021	21	10000	0	20	10000	0	70	0	1548887	10020	20	0	10004	20	10000	11	10000	10
10024	120033	10021	21	10000	0	20	10000	0	70	0	1548887	10020	20	0	10000	20	10000	11	10000	10
10025	120066	10023	21	10002	0	20	10015	0	70	0	1548887	10020	20	0	10000	20	10000	11	10000	10
10024	120033	10021	21	10000	0	20	10000	0	66	0	1549059	10035	20	0	10029	20	10000	11	10000	10
10024	120033	10021	21	10000	0	20	10000	0	70	0	1548887	10020	20	0	10000	20	10000	11	10000	10
10025	120066	10023	21	10002	0	20	10015	0	70	0	1548887	10020	20	0	10000	20	10000	11	10000	10
10024	120033	10021	21	10000	0	20	10000	0	70	0	1548887	10020	20	0	10000	20	10000	11	10000	10
10024	120033	10021	21	10000	0	20	10000	0	70	0	1548887	10020	20	0	10000	20	10029	11	10000	10
10113	120924	10133	80	10006	47	78	10045	0	70	0	1548887	10020	20	0	10000	20	10000	11	10000	10
10024	120033	10021	21	10000	0	20	10000	0	70	0	1548887	10020	20	0	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  fsqrt v0.4s, v8.4s
  fsqrt v1.4s, v8.4s
  fsqrt v2.4s, v8.4s
  fsqrt v3.4s, v8.4s
  fsqrt v4.4s, v8.4s
  fsqrt v5.4s, v8.4s
  fsqrt v6.4s, v8.4s
  fsqrt v7.4s, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80004	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80032	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80004	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80064	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80004	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80031	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80004	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079873	80119	200	0	80032	200	0	80004	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079608	80100	200	0	80004	200	0	80004	1	0	80000	100
80204	320041	80101	101	80000	0	100	80000	0	300	0	4079873	80119	200	0	80035	200	0	80004	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	320041	80021	21	80000	20	80000	0	70	0	4079608	80020	20	0	80000	20	0	80000	11	0	80000	10
80025	320082	80027	21	80006	20	80019	0	70	0	4079608	80020	20	0	80000	20	0	80000	11	0	80000	10
80024	320041	80021	21	80000	20	80000	0	70	0	4079608	80020	20	0	80000	20	0	80026	11	0	80000	10
80025	320082	80027	21	80006	20	80019	0	70	0	4079608	80020	20	0	80004	20	0	80000	11	0	80000	10
80024	320041	80021	21	80000	20	80000	0	70	0	4079608	80020	20	0	80000	20	0	80030	11	0	80000	10
80024	320041	80021	21	80000	20	80000	0	70	0	4079608	80020	20	0	80000	20	0	80000	11	0	80000	10
80024	320041	80021	21	80000	20	80000	0	70	0	4079608	80020	20	0	80000	20	0	80032	11	0	80000	10
80024	320041	80021	21	80000	20	80000	0	70	0	4079608	80020	20	0	80004	20	0	80000	11	0	80000	10
80024	320041	80021	21	80000	20	80000	0	70	0	4079873	80039	20	0	80034	20	0	80000	11	0	80000	10
80024	320041	80021	21	80000	20	80000	0	70	0	4079608	80020	20	0	80000	20	0	80035	11	0	80000	10

FSQRT (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations