Icestorm: FSQRT (vector, 8H) measurements

Code:

  fsqrt v0.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fsqrt v0.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10006	200	0	10006	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289241	10115	200	10030	200	0	10004	1	0	10000	100
10682	102393	10565	390	10002	173	347	10015	300	1289413	10130	200	10053	3853	2384	10049	1671	1279	10002	2362
10205	100066	10103	101	10002	0	100	10015	300	1289241	10115	200	10029	204	0	10096	3	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100033	10101	101	10000	0	100	10000	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10204	100128	10107	101	10006	0	100	10030	300	1289069	10100	200	10004	200	0	10004	1	0	10000	100
10205	100066	10103	101	10002	0	100	10015	300	1289241	10115	200	10028	200	0	10004	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10006	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10025	100066	10023	21	10002	20	10015	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10000	11	10000	10
10025	100066	10023	21	10002	20	10015	70	1289069	10020	20	10000	20	10000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	10032	11	10000	10

Test 3: throughput

Count: 8

Code:

  fsqrt v0.8h, v8.8h
  fsqrt v1.8h, v8.8h
  fsqrt v2.8h, v8.8h
  fsqrt v3.8h, v8.8h
  fsqrt v4.8h, v8.8h
  fsqrt v5.8h, v8.8h
  fsqrt v6.8h, v8.8h
  fsqrt v7.8h, v8.8h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80004	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80032	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80004	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80032	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80004	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80032	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80004	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80004	1	80000	100
80204	320039	80101	101	80000	0	100	80000	300	4079608	80100	200	80004	200	80004	1	80000	100
80205	320078	80107	101	80006	0	100	80019	300	4079608	80100	200	80004	200	80004	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	320039	80021	21	80000	0	20	80000	70	4079608	80020	20	80004	20	0	80000	11	0	80000	10
80025	320078	80027	21	80006	0	20	80019	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80024	320039	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80025	320078	80027	21	80006	0	20	80019	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80024	320039	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80025	320078	80027	21	80006	0	20	80019	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80024	320039	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80032	11	0	80000	10
80025	320078	80027	21	80006	0	20	80019	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80024	320039	80021	21	80000	0	20	80000	70	4079608	80020	20	80000	20	0	80000	11	0	80000	10
80025	320078	80027	21	80006	0	20	80019	70	4079608	80020	20	80000	20	0	80032	11	0	80000	10

FSQRT (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations