Icestorm: INS (element, B) measurements

Code:

  ins v0.b[2], v1.b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  ins v0.b[2], v1.b[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	66	509580	10054	20	10048	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  ins v0.b[2], v0.b[1]

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.b[2], v8.b[1]
  movi v1.16b, 0
  ins v1.b[2], v8.b[1]
  movi v2.16b, 0
  ins v2.b[2], v8.b[1]
  movi v3.16b, 0
  ins v3.b[2], v8.b[1]
  movi v4.16b, 0
  ins v4.b[2], v8.b[1]
  movi v5.16b, 0
  ins v5.b[2], v8.b[1]
  movi v6.16b, 0
  ins v6.b[2], v8.b[1]
  movi v7.16b, 0
  ins v7.b[2], v8.b[1]

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40555	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160026	1	0	160000	100
160204	40106	80110	101	80009	100	80013	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320204	80150	200	80050	200	0	160026	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	0	160026	1	0	160000	100
160204	40101	80110	101	80009	100	80013	300	320052	80112	200	80012	200	0	160024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43875	80020	11	80009	10	80013	30	320052	80022	20	80012	20	160026	1	160000	10
160024	41243	80020	11	80009	10	80013	30	320056	80023	20	80013	20	160000	1	160000	10
160024	40432	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40386	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40425	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40390	80011	11	80000	10	80000	30	320192	80057	20	80047	20	160000	1	160000	10
160024	40438	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  ins v0.b[2], v16.b[1]
  ins v1.b[2], v16.b[1]
  ins v2.b[2], v16.b[1]
  ins v3.b[2], v16.b[1]
  ins v4.b[2], v16.b[1]
  ins v5.b[2], v16.b[1]
  ins v6.b[2], v16.b[1]
  ins v7.b[2], v16.b[1]
  ins v8.b[2], v16.b[1]
  ins v9.b[2], v16.b[1]
  ins v10.b[2], v16.b[1]
  ins v11.b[2], v16.b[1]
  ins v12.b[2], v16.b[1]
  ins v13.b[2], v16.b[1]
  ins v14.b[2], v16.b[1]
  ins v15.b[2], v16.b[1]

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80088	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	320028	1	160000	100
160204	80034	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160107	101	160006	100	160010	0	300	0	640200	160152	200	0	160060	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320120	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80119	160015	11	160004	0	10	160008	30	640044	160020	20	160014	20	320028	1	160000	10
160024	80044	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160025	80069	160053	11	160042	0	10	160054	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

INS (element, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations