Icestorm: INS (element, H) measurements

Code:

  ins v0.h[2], v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2085	1013	1	1012	1036	50248	1000	1000	2000	1	1000
1004	2084	1013	1	1012	1036	50248	1000	1000	2000	1	1000
1004	2085	1013	1	1012	1036	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50780	1036	1043	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2082	1	1000
1004	2084	1013	1	1012	1036	50780	1036	1042	2000	1	1000

Test 2: Latency 1->1

Code:

  ins v0.h[2], v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10006	200	20012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	0	20	10000	70	509247	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10025	20066	10029	21	10008	0	20	10034	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	69	509564	10054	20	10049	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  ins v0.h[2], v0.h[1]

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	300	509580	10134	200	10046	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	202	0	20094	2	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.h[2], v8.h[1]
  movi v1.16b, 0
  ins v1.h[2], v8.h[1]
  movi v2.16b, 0
  ins v2.h[2], v8.h[1]
  movi v3.16b, 0
  ins v3.h[2], v8.h[1]
  movi v4.16b, 0
  ins v4.h[2], v8.h[1]
  movi v5.16b, 0
  ins v5.h[2], v8.h[1]
  movi v6.16b, 0
  ins v6.h[2], v8.h[1]
  movi v7.16b, 0
  ins v7.h[2], v8.h[1]

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40450	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40108	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40099	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320204	80150	200	80050	200	160026	1	160000	100
160204	40108	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5050

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43881	80020	11	80009	10	80013	30	320000	80010	20	80000	20	160000	1	160000	10
160024	41253	80011	11	80000	10	80000	30	320188	80056	20	80046	20	160000	1	160000	10
160024	40455	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40414	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40373	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40400	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40383	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40375	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40361	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40400	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  ins v0.h[2], v16.h[1]
  ins v1.h[2], v16.h[1]
  ins v2.h[2], v16.h[1]
  ins v3.h[2], v16.h[1]
  ins v4.h[2], v16.h[1]
  ins v5.h[2], v16.h[1]
  ins v6.h[2], v16.h[1]
  ins v7.h[2], v16.h[1]
  ins v8.h[2], v16.h[1]
  ins v9.h[2], v16.h[1]
  ins v10.h[2], v16.h[1]
  ins v11.h[2], v16.h[1]
  ins v12.h[2], v16.h[1]
  ins v13.h[2], v16.h[1]
  ins v14.h[2], v16.h[1]
  ins v15.h[2], v16.h[1]

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80097	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80034	160107	101	160006	0	100	160010	300	640204	160153	200	160063	200	320028	1	160000	100
160204	80035	160107	101	160006	0	100	160010	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80034	160107	101	160006	0	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640192	160150	200	160058	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80205	160015	11	160004	10	160008	0	30	0	640044	160020	20	0	160014	20	0	320128	1	0	160000	10
160024	80124	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320122	1	0	160000	10
160024	80039	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10

INS (element, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations