Icestorm: INS (general, B) measurements

Code:

  ins v0.b[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1040	2080	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000

Test 2: Latency 1->1

Code:

  ins v0.b[2], w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20204	20035	20103	101	10000	10002	100	10000	10003	300	30009	509314	20103	200	10005	10005	200	10005	20010	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10003	300	30009	509314	20103	200	10005	10005	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10044	20088	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20024	20035	20013	11	10000	10002	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10040	30	30176	509712	20084	20	10044	10044	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10

Test 3: Latency 1->2 roundtrip

Code:

  ins v0.b[2], w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 9.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	90030	40101	10101	20000	10000	100	20000	10001	300	1376322	2318460	30101	200	10002	20004	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30205	90063	40108	10103	20003	10002	100	20029	10001	300	1376328	2318460	30101	200	10002	20004	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90056	40101	10101	20000	10000	100	20000	10000	300	1376426	2318616	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 9.0063

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30025	90066	40018	10013	20003	10002	10	20029	10000	30	1376537	2318798	30010	20	10002	20002	20	10002	30006	10001	10000	10000	10010
30024	90232	40033	10017	20010	10006	10	20060	10124	30	1382854	2329396	30344	20	10131	20258	20	10112	30326	10017	10000	10000	10010
30024	90034	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10002	30003	10001	10000	10000	10010
30024	90670	40087	10031	20035	10021	10	20210	10106	30	1383787	2330902	30296	20	10113	20223	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10018	30	1376507	2318738	30056	20	10021	20039	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10019	30	1376547	2318813	30058	20	10022	20042	20	10000	30000	10001	10000	10000	10010
30025	90160	40028	10015	20008	10005	10	20058	10000	30	1376589	2318876	30010	20	10000	20000	20	10168	30491	10025	10000	10000	10010
30024	90551	40065	10025	20025	10015	10	20150	10000	30	1376379	2318538	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30025	90063	40018	10013	20003	10002	10	20029	10018	30	1376687	2319024	30056	20	10021	20039	20	10000	30000	10001	10000	10000	10010
30024	90329	40044	10020	20015	10009	10	20090	10179	30	1386673	2335490	30489	20	10185	20364	20	10075	30222	10012	10000	10000	10010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.b[2], w8
  movi v1.16b, 0
  ins v1.b[2], w8
  movi v2.16b, 0
  ins v2.b[2], w8
  movi v3.16b, 0
  ins v3.b[2], w8
  movi v4.16b, 0
  ins v4.b[2], w8
  movi v5.16b, 0
  ins v5.b[2], w8
  movi v6.16b, 0
  ins v6.b[2], w8
  movi v7.16b, 0
  ins v7.b[2], w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240204	60342	160111	101	80004	80006	100	80008	80008	300	240024	629551	160116	200	80008	80008	202	80038	160074	2	80000	160000	100
240204	60249	160111	101	80004	80006	100	80008	80008	300	240024	629802	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240064	622586	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60103	160111	101	80004	80006	100	80008	80008	300	240196	630155	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60101	160112	101	80005	80006	100	80008	80008	300	240064	629811	160116	200	80008	80008	200	80008	160016	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7531

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240024	61894	160022	11	80005	80006	10	80009	80009	30	240027	628377	160027	20	80009	80008	20	80000	160000	1	80000	160000	10
240024	60609	160011	11	80000	80000	10	80000	80000	30	240000	623130	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60236	160011	11	80000	80000	10	80000	80000	30	240000	623247	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	61218	160022	11	80005	80006	10	80008	80000	30	240000	623445	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60236	160011	11	80000	80000	10	80000	80000	30	240000	623370	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60217	160011	11	80000	80000	10	80000	80000	30	240000	623423	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60222	160011	11	80000	80000	10	80000	80000	30	240000	623539	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60239	160011	11	80000	80000	10	80000	80000	30	240000	623353	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60246	160011	11	80000	80000	10	80000	80000	30	240000	623381	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60220	160011	11	80000	80000	10	80000	80000	30	240000	623622	160010	20	80000	80000	20	80000	160000	1	80000	160000	10

INS (general, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations