Icestorm: INS (general, D) measurements

Code:

  ins v0.d[1], x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000
2004	2035	2001	1	1000	1000	1000	1000	3000	50314	2000	1000	1000	1000	2000	1	1000	1000

Test 2: Latency 1->1

Code:

  ins v0.d[1], x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20204	20035	20104	101	10000	10003	100	10000	10003	300	30009	509314	20103	200	10005	10005	200	10005	20010	1	10000	10000	100
20204	20035	20104	101	10000	10003	100	10000	10002	300	30012	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10164	314	33292	511705	20412	204	10166	10166	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100
20204	20035	20103	101	10000	10002	100	10000	10002	300	30006	509314	20102	200	10004	10004	200	10004	20008	1	10000	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20024	20035	20013	11	10000	10002	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30000	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30006	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10
20024	20035	20011	11	10000	10000	10	10000	10000	30	30004	509314	20010	20	10000	10000	20	10000	20000	1	10000	10000	10

Test 3: Latency 1->2 roundtrip

Code:

  ins v0.d[1], x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 9.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	90030	40101	10101	20000	10000	100	20000	10001	300	1376322	2318460	30101	200	10002	20004	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376345	2318486	30100	200	10002	20002	200	10022	30063	10003	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376360	2318512	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30205	90063	40108	10103	20003	10002	100	20029	10000	300	1376835	2319266	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100
30204	90049	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	30003	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 9.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30025	90063	40018	10013	20003	10002	10	20029	10000	30	1376338	2318486	30010	20	10002	20002	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10018	30	1376498	2318738	30056	20	10021	20039	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	30000	10001	10000	10000	10010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ins v0.d[1], x8
  movi v1.16b, 0
  ins v1.d[1], x8
  movi v2.16b, 0
  ins v2.d[1], x8
  movi v3.16b, 0
  ins v3.d[1], x8
  movi v4.16b, 0
  ins v4.d[1], x8
  movi v5.16b, 0
  ins v5.d[1], x8
  movi v6.16b, 0
  ins v6.d[1], x8
  movi v7.16b, 0
  ins v7.d[1], x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240205	60428	160172	101	80035	80036	100	80039	80008	300	240083	629385	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60105	160111	101	80004	80006	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60101	160111	101	80004	80006	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240082	629756	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60092	160110	101	80004	80005	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100
240204	60097	160111	101	80004	80006	100	80008	80008	300	240024	629902	160116	200	80008	80008	200	80008	160016	1	80000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7530

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240024	62198	160021	11	80004	80006	10	80008	80000	30	240000	628522	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60603	160011	11	80000	80000	10	80000	80000	30	240078	624380	160010	20	80000	80000	20	80038	160076	1	80000	160000	10
240024	60371	160011	11	80000	80000	10	80000	80000	30	240127	624254	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60256	160011	11	80000	80000	10	80000	80000	30	240041	623291	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60259	160011	11	80000	80000	10	80000	80000	30	240000	623164	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60477	160011	11	80000	80000	10	80000	80000	30	240000	623226	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60242	160011	11	80000	80000	10	80000	80000	30	240064	624232	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60280	160011	11	80000	80000	10	80000	80000	30	240035	626252	160010	20	80000	80000	20	80000	160000	1	80000	160000	10
240024	60341	160069	11	80029	80029	10	80029	80000	30	240026	623321	160010	20	80000	80000	20	80029	160058	1	80000	160000	10
240024	60239	160011	11	80000	80000	10	80000	80038	30	240307	627275	160086	20	80038	80038	20	80000	160000	1	80000	160000	10

INS (general, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations