Icestorm: LD1R (16B) measurements

Code:

  ld1r { v0.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29587	2017	1	1014	1002	1002	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29396	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29451	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29431	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29405	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29417	2003	1	1002	1000	1000	1000	3001	7774	2000	1000	1000	1000	1000	1	1000	1000
62004	29435	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29417	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62005	29488	2004	1	1002	1001	1001	1000	3000	7769	2000	1000	1000	1000	1000	1	1000	1000
62004	29683	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.16b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120155	70114	40101	20012	10001	30130	20031	10004	3208879	1257514	2575551	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10015	3209323	1257794	2576087	60180	30248	10016	20032	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60294	10016	20033	40006	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10015	3210377	1305595	2625390	60177	30248	10016	20033	60298	10016	20033	40006	10000	10000	40100
60206	120126	70125	40111	20012	10002	30163	20055	10004	3209071	1257727	2575941	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120149	70024	40011	20012	10001	30040	20030	10004	3209073	1259243	2578632	60024	30032	10004	20008	60020	10000	20000	40001	10000	10000	40010
60025	120166	70026	40016	20009	10001	30040	20024	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60025	120082	70024	40016	20007	10001	30043	20031	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10004	3209755	1259590	2579327	60024	30032	10004	20008	60122	10016	20033	40009	10000	10000	40010
60024	120049	70015	40011	20004	10000	30013	20007	10004	3209134	1259336	2578799	60024	30032	10004	20008	60020	10000	20000	40001	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3209033	1259242	2578610	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.16b }, [x6]
  ld1r { v0.16b }, [x6]
  ld1r { v0.16b }, [x6]
  ld1r { v0.16b }, [x6]
  ld1r { v0.16b }, [x6]
  ld1r { v0.16b }, [x6]
  ld1r { v0.16b }, [x6]
  ld1r { v0.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40266	160267	101	80128	80038	100	80038	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80054	80054	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40107	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	255438	659582	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	40668	160179	11	80129	80039	10	80039	80012	30	251744	660616	160034	20	80012	80012	20	80000	80000	1	80000	80000	10
160024	40106	160049	11	80038	80000	10	80000	80000	30	339585	772509	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40065	160049	11	80038	80000	10	80000	80054	30	240502	653076	160118	20	80054	80054	20	80000	80000	1	80000	80000	10
160024	40072	160049	11	80038	80000	10	80000	80000	30	309172	733551	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160025	40158	160120	11	80071	80038	10	80055	80013	30	240321	641292	160036	20	80013	80013	20	80000	80000	1	80000	80000	10
160024	40066	160047	11	80036	80000	10	80000	80000	30	277302	693613	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40069	160047	11	80036	80000	10	80000	80000	30	318101	742426	160010	20	80000	80000	20	80055	80055	1	80000	80000	10

LD1R (16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations