Icestorm: LD1R (1D) measurements

Code:

  ld1r { v0.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29559	2017	1	1014	1002	1002	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29358	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29347	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29343	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29335	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29338	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29337	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29344	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29335	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1001	1001	1	1000	1000
62004	29355	2006	1	1005	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.1d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120151	70114	40101	20012	10001	30130	20030	10714	3230997	1266509	2576600	61935	31750	10819	20033	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10015	3210538	1258322	2577119	60180	30251	10016	20033	60224	10004	20008	40001	10000	10000	40100
60204	120048	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60298	10016	20033	40006	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10015	3209300	1267369	2585874	60177	30248	10016	20033	60224	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60026	120243	70033	40016	20015	10002	30070	20054	10004	3209755	1259589	2579328	60024	30032	10004	20008	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10014	3209466	1259443	2579014	60086	30067	10016	20033	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10016	3210681	1259968	2580038	60090	30071	10016	20033	60020	10000	20000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.1d }, [x6]
  ld1r { v0.1d }, [x6]
  ld1r { v0.1d }, [x6]
  ld1r { v0.1d }, [x6]
  ld1r { v0.1d }, [x6]
  ld1r { v0.1d }, [x6]
  ld1r { v0.1d }, [x6]
  ld1r { v0.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40281	160267	101	80128	80038	100	80038	80012	300	240268	641164	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160139	101	80030	80008	100	80012	80012	300	246590	649323	160124	200	80012	80012	200	80013	80013	1	80000	80000	100
160204	40123	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240202	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240202	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80054	80054	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	40319	160065	11	80045	80009	10	80013	80000	30	240232	641068	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40091	160049	11	80038	80000	10	80000	80054	30	285975	705060	160118	20	80054	80054	20	80126	80126	1	80000	80000	10
160024	40126	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240106	652382	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	646284	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	267192	695517	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40099	160049	11	80038	80000	10	80000	80126	30	273372	685300	160262	20	80126	80126	20	80000	80000	1	80000	80000	10
160024	40063	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40054	160035	11	80024	80000	10	80000	80000	30	240232	642188	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

LD1R (1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations