Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1R (2D)

Test 1: uops

Code:

  ld1r { v0.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
62005296732017110141002100210003000776720001000100010001000110001000
62004294632003110021000100010003000776720001000100010001000110001000
62004294872003110021000100010003000776720001000100010001000110001000
62004294282003110021000100010003000776720001000100010001000110001000
62004294452003110021000100010003000776720001000100010001000110001000
62004294712003110021000100010003000776720001000100010001000110001000
62004294782003110021000100010003000776720001000100010001000110001000
62004295022003110021000100010003000776720001000100010001000110001000
62004294222003110021000100010003000776720001000100010001000110001000
62004301162003110021000100010003000777020001000100010001000110001000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
60205120159701144010120012100013013020031100043208937125753625755976011430212100042000860302100162003340006100001000040100
60204120056701054010120004100003010320007100043209017125770525758976011430212100042000860224100042000840001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100042000840001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100042000840001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100042000840001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860302100162003340006100001000040100
60204120049701054010120004100003010320007100043209125125775025759866011430212100042000860224100042000840001100001000040100
60204120049701054010120004100003010320007100043209098125773825759666011430212100042000860224100042000840001100001000040100
60204120049701054010120004100003010320007100043209071125772725759416011430212100042000860224100042000840001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100042000840001100001000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
60026120193700334001620015100023007020056100043209350125943225789826002430032100042000860020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60025120082700244001620007100013004320029100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120051700154001120004100003001020000100003209114125927525786786001030020100002000060020100002000040001100001000040010
60024120050700154001120004100003001020000100003209222125932225787696001030020100002000060122100162003340006100001000040010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020540310160267101801288003810080038800123002402046404201601242008001280012200800128001218000080000100
16020440112160135101800268000810080012800123002402046404201601242008001280012200800128001218000080000100
16020440101160135101800268000810080012800123002402046404201601242008001280012200800128001218000080000100
16020440101160135101800268000810080012800123002402046404201601242008001280012200800128001218000080000100
16020440101160135101800268000810080012800123002402026404201601242008001280012200800128001218000080000100
16020440101160135101800268000810080012800123002402046404201601242008001280012200800128001218000080000100
16020440101160135101800268000810080012800123002402026404201601242008001280012200800128001218000080000100
16020440101160135101800268000810080012800543002582386637121602082008005480054200800128001218000080000100
16020440103160135101800268000810080012800123002462486476561601242008001280012200800128001218000080000100
16020440108160135101800268000810080012800123002402046404201601242008001280012200800128001218000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002540424160177118012880038108003880012302402786406601600342080012800122080000800001800008000010
16002440079160047118003680000108000080000302401686403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401666403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401666403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401686403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401666403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401686403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401686403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401666403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401686403401600102080000800002080000800001800008000010