Icestorm: LD1R (2D) measurements

Code:

  ld1r { v0.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29673	2017	1	1014	1002	1002	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29463	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29487	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29428	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29445	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29471	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29478	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29502	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29422	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	30116	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120159	70114	40101	20012	10001	30130	20031	10004	3208937	1257536	2575597	60114	30212	10004	20008	60302	10016	20033	40006	10000	10000	40100
60204	120056	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60302	10016	20033	40006	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209125	1257750	2575986	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209098	1257738	2575966	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209071	1257727	2575941	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60026	120193	70033	40016	20015	10002	30070	20056	10004	3209350	1259432	2578982	60024	30032	10004	20008	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60025	120082	70024	40016	20007	10001	30043	20029	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120051	70015	40011	20004	10000	30010	20000	10000	3209114	1259275	2578678	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120050	70015	40011	20004	10000	30010	20000	10000	3209222	1259322	2578769	60010	30020	10000	20000	60122	10016	20033	40006	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]
  ld1r { v0.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40310	160267	101	80128	80038	100	80038	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40112	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240202	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80012	300	240202	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160135	101	80026	80008	100	80012	80054	300	258238	663712	160208	200	80054	80054	200	80012	80012	1	80000	80000	100
160204	40103	160135	101	80026	80008	100	80012	80012	300	246248	647656	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40108	160135	101	80026	80008	100	80012	80012	300	240204	640420	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	40424	160177	11	80128	80038	10	80038	80012	30	240278	640660	160034	20	80012	80012	20	80000	80000	1	80000	80000	10
160024	40079	160047	11	80036	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240166	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240166	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240166	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240166	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

LD1R (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations