Icestorm: LD1R (2S) measurements

Code:

  ld1r { v0.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29829	2017	1	1014	1002	1002	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29589	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29518	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29448	2003	1	1002	1000	1000	1000	3000	7768	2000	1000	1000	1000	1000	1	1000	1000
62004	29560	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29685	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29745	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29523	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29622	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29556	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120152	70114	40101	20012	10001	30130	20031	10004	3208937	1257536	2575597	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120052	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120055	70105	40101	20004	10000	30103	20007	10004	3209179	1257773	2576032	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10016	3209376	1257829	2576151	60180	30251	10016	20033	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209071	1257727	2575943	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120051	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120159	70024	40011	20012	10001	30040	20031	10016	3209420	1259359	2578865	60090	30071	10016	20033	60044	10004	20008	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.2s }, [x6]
  ld1r { v0.2s }, [x6]
  ld1r { v0.2s }, [x6]
  ld1r { v0.2s }, [x6]
  ld1r { v0.2s }, [x6]
  ld1r { v0.2s }, [x6]
  ld1r { v0.2s }, [x6]
  ld1r { v0.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5014

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40287	160267	101	80128	80038	100	80038	80012	300	240268	641164	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40113	160153	101	80044	80008	100	80012	80012	300	240268	641892	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160153	101	80044	80008	100	80012	80012	300	240268	641892	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160153	101	80044	80008	100	80012	80012	300	291601	701925	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40130	160153	101	80044	80008	100	80012	80054	300	270199	678252	160208	200	80054	80054	200	80012	80012	1	80000	80000	100
160204	40117	160153	101	80044	80008	100	80012	80012	300	240268	641892	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160153	101	80044	80008	100	80012	80012	300	240268	641892	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160153	101	80044	80008	100	80012	80012	300	240268	641892	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160153	101	80044	80008	100	80012	80012	300	240268	641892	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160153	101	80044	80008	100	80012	80012	300	258220	663922	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	40606	160177	11	80128	80038	10	80038	80012	30	240204	640420	160034	20	80012	80012	20	80000	80000	1	80000	80000	10
160024	40063	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80055	80055	1	80000	80000	10
160024	40161	160031	11	80020	80000	10	80000	81067	65449	360269	751746	163017	2566	81264	80065	20	80054	80054	1	80000	80000	10
160024	40059	160033	11	80022	80000	10	80000	80000	30	287968	704117	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40058	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40060	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240166	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

LD1R (2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations