Icestorm: LD1R (4H) measurements

Code:

  ld1r { v0.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29953	2018	1	1015	1002	1002	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29495	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29479	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29463	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62005	29477	2005	1	1003	1001	1001	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29450	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29503	2003	1	1002	1000	1000	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29470	2003	1	1002	1000	1000	1000	3002	7772	2000	1000	1000	1000	1000	1	1000	1000
62004	30262	2003	1	1002	1000	1000	1000	3000	7793	2000	1000	1000	1000	1000	1	1000	1000
62004	29544	2003	1	1002	1000	1000	1000	3001	7771	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.4h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120176	70114	40101	20012	10001	30130	20031	10004	3208956	1257613	2575730	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60205	120080	70114	40106	20007	10001	30133	20031	10004	3208917	1257595	2575694	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10016	3209290	1257729	2575969	60180	30251	10016	20033	60224	10004	20008	40001	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3208963	1257683	2575851	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60205	120080	70114	40106	20007	10001	30133	20030	10004	3209422	1257873	2576228	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60205	120080	70114	40106	20007	10001	30133	20030	10004	3209341	1257844	2576166	60114	30212	10004	20008	60294	10016	20033	40006	10000	10000	40100
60204	120047	70105	40101	20004	10000	30103	20007	10004	3210529	1258350	2577156	60114	30212	10004	20008	60302	10016	20033	40006	10000	10000	40100
60204	120064	70105	40101	20004	10000	30103	20007	10016	3209315	1271633	2590244	60179	30250	10016	20033	60224	10004	20008	40001	10000	10000	40100
60205	120080	70114	40106	20007	10001	30133	20031	10004	3209341	1257840	2576162	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60205	120136	70114	40106	20007	10001	30133	20029	10004	3209044	1257719	2575920	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120158	70024	40011	20012	10001	30040	20031	10004	3208911	1259177	2578494	60024	30032	10004	20008	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10011	3210745	1259929	2579972	60074	30057	10012	20025	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10016	3210390	1259854	2579804	60090	30071	10016	20033	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60025	120075	70022	40016	20005	10001	30043	20031	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120042	70013	40011	20002	10000	30010	20000	10000	3208898	1259187	2578495	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.4h }, [x6]
  ld1r { v0.4h }, [x6]
  ld1r { v0.4h }, [x6]
  ld1r { v0.4h }, [x6]
  ld1r { v0.4h }, [x6]
  ld1r { v0.4h }, [x6]
  ld1r { v0.4h }, [x6]
  ld1r { v0.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40282	160269	101	80129	80039	100	80039	80012	300	240278	640660	160124	200	80012	80012	202	80056	80056	2	80000	80000	100
160204	40122	160150	101	80041	80008	100	80012	80013	300	240343	640860	160126	200	80013	80013	200	80012	80012	1	80000	80000	100
160204	40116	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	40673	160177	11	80128	80038	10	80038	80000	30	240232	641068	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40081	160049	11	80038	80000	10	80000	80000	30	240232	646812	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160025	40122	160125	11	80075	80039	10	80055	80000	30	284099	695959	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160049	11	80038	80000	10	80000	80000	30	267744	696072	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

LD1R (4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations